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Mar 12 2024

bofh added a comment to D44292: website/administrations: Refactor.

@bcr Do you have any objections on behalf of core@? As I am removing some stale members I was also looking forward for core's approval.

Mar 12 2024, 5:45 PM · Core Team, doceng

Mar 10 2024

bcr accepted D44292: website/administrations: Refactor.
Mar 10 2024, 2:50 PM · Core Team, doceng
bofh requested review of D44292: website/administrations: Refactor.
Mar 10 2024, 2:17 PM · Core Team, doceng

Oct 21 2022

bofh removed a watcher for Core Team: bofh.
Oct 21 2022, 6:50 PM

Aug 26 2022

eduardo added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

patch ready and tested at PR 265632

Aug 26 2022, 4:53 PM · Core Team

Aug 25 2022

eduardo added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

How can I find device id for this legion like

#define	LENOVO_L5AMD_SUBVENDOR	HDA_MODEL_CONSTRUCT(LENOVO, 0x381b)

Thanks

In my case I ran pciconf -lv and found a device with multimedia class:

hdac0@pci0:0:31:3:      class=0x040380 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa171 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = 'CM238 HD Audio Controller'
    class      = multimedia
    subclass   = HDA

The subdevice=0x15e0 part turned out to be the correct value for that switch.

Aug 25 2022, 9:40 PM · Core Team
arrowd added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

How can I find device id for this legion like

#define	LENOVO_L5AMD_SUBVENDOR	HDA_MODEL_CONSTRUCT(LENOVO, 0x381b)

Thanks

Aug 25 2022, 8:53 PM · Core Team
eduardo added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

it works same way for a legion 5 intel version:

Aug 25 2022, 6:49 PM · Core Team

Jun 26 2022

lwhsu added members for Core Team: 0mp, bcr, grog, jhb, lwhsu, tcberner, manu.
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Mar 25 2022

scottl removed a member for Core Team: scottl.
Mar 25 2022, 10:10 PM

Jan 25 2022

eduardo added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

I'm trying to get sound from my speakers on a Lenovo 5 (intel i7), headphones works ok.

Jan 25 2022, 8:30 AM · Core Team

Jan 23 2022

emaste closed D30333: sound: add patch for Lenovo Legion 5 AMD..
Jan 23 2022, 8:05 PM · Core Team

Jun 1 2021

trasz added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

FWIW, splice: https://reviews.freebsd.org/D30597

Jun 1 2021, 3:33 PM · Linux Emulation, Core Team

May 26 2021

arrowd added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

Done: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=256169

May 26 2021, 1:56 PM · Core Team

May 25 2021

emaste added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

we have so many such unfinished things

May 25 2021, 5:47 PM · Linux Emulation, Core Team
dchagin added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

FWIW, splice(2) can be a wrapper around copy_file_range(2). We should also have a fallback from sendfile(2) to splice(2), for when it fails with ENOTSOCK. This is one of the things that break Mono

May 25 2021, 5:42 PM · Linux Emulation, Core Team
dchagin added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

Why do we need it? All the BSD's seem to exist without splice() just fine?

May 25 2021, 5:25 PM · Linux Emulation, Core Team
dchagin added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

The most pressing issue is the incomplete pthread support notably with FUTEX_LOCK_PI and FUTEX_UNLOCK_PI and friends.

https://wiki.freebsd.org/Linuxulator#Roadmap, pi is not the key, we have so many important holes

It's literally the second item on that list, for example pulseaudio hard crashes because it's not there. I have started but it's pretty hard, I wonder if anyone can help?

May 25 2021, 5:18 PM · Linux Emulation, Core Team
trasz added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

FWIW, splice(2) can be a wrapper around copy_file_range(2). We should also have a fallback from sendfile(2) to splice(2), for when it fails with ENOTSOCK. This is one of the things that break Mono.

May 25 2021, 5:07 PM · Linux Emulation, Core Team
pitwuu_gmail.com added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

we have so many such unfinished things, like arm linuxulator, splice sys call....

Yes, about splice, I was thinking we could just use a regular copy and be done with it. It wouldn't be that hard to implement, I can possibly look at it.

some time ago I wrote splice emulation via dofileread/dofilewrite ) but I abandoned it because I think we need a native splice() and tee() implementation. feel free to as arch@ about it:)

May 25 2021, 5:02 PM · Linux Emulation, Core Team
pitwuu_gmail.com added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

we have so many such unfinished things, like arm linuxulator, splice sys call....

Yes, about splice, I was thinking we could just use a regular copy and be done with it. It wouldn't be that hard to implement, I can possibly look at it.

some time ago I wrote splice emulation via dofileread/dofilewrite ) but I abandoned it because I think we need a native splice() and tee() implementation. feel free to as arch@ about it:)

The most pressing issue is the incomplete pthread support notably with FUTEX_LOCK_PI and FUTEX_UNLOCK_PI and friends.

https://wiki.freebsd.org/Linuxulator#Roadmap, pi is not the key, we have so many important holes

May 25 2021, 4:59 PM · Linux Emulation, Core Team
emaste added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

I don't think they are even usable, since the core file is in FreeBSD format that linux gdb can't parse, and confuse the freebsd gdb because it's a linux process/elf.

May 25 2021, 4:56 PM · Linux Emulation, Core Team
dchagin added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

we have so many such unfinished things, like arm linuxulator, splice sys call....

Yes, about splice, I was thinking we could just use a regular copy and be done with it. It wouldn't be that hard to implement, I can possibly look at it.

May 25 2021, 4:55 PM · Linux Emulation, Core Team
pitwuu_gmail.com added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

Encountered in the crash handler of 'kodi'. Kodi still crashes, but at least the crash handler doesn't seem to crash anymore.

IMO this sort of thing is sufficient reason to have this linprocfs entry. What do you think about extending it slightly, at least translating FreeBSD's default %N.core to the Linux equivalent (%e.core I guess?)

we have so many such unfinished things, like arm linuxulator, splice sys call....

May 25 2021, 4:47 PM · Linux Emulation, Core Team
pitwuu_gmail.com added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..
lots of output
May 25 2021, 4:40 PM · Core Team
dchagin added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

Encountered in the crash handler of 'kodi'. Kodi still crashes, but at least the crash handler doesn't seem to crash anymore.

IMO this sort of thing is sufficient reason to have this linprocfs entry. What do you think about extending it slightly, at least translating FreeBSD's default %N.core to the Linux equivalent (%e.core I guess?)

May 25 2021, 4:40 PM · Linux Emulation, Core Team
pitwuu_gmail.com added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

Encountered in the crash handler of 'kodi'. Kodi still crashes, but at least the crash handler doesn't seem to crash anymore.

IMO this sort of thing is sufficient reason to have this linprocfs entry. What do you think about extending it slightly, at least translating FreeBSD's default %N.core to the Linux equivalent (%e.core I guess?)

May 25 2021, 4:35 PM · Linux Emulation, Core Team
emaste added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

Encountered in the crash handler of 'kodi'. Kodi still crashes, but at least the crash handler doesn't seem to crash anymore.

May 25 2021, 4:25 PM · Linux Emulation, Core Team
pitwuu_gmail.com added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

Is there a way to config git to do that by default? It's annoying to do every time.

I'm not sure, although I also suspect you don't want it when generating a patch for your own review, not for upload to Phabricator. There is a tool in the tree, tools/tools/git/git-arc, which can take care of submitting phab reviews for you.

May 25 2021, 4:23 PM · Linux Emulation, Core Team
emaste added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

Is there a way to config git to do that by default? It's annoying to do every time.

May 25 2021, 4:19 PM · Linux Emulation, Core Team
pitwuu_gmail.com added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

For future uploads please include full context by using e.g. git show -U99999 <hash> - see https://wiki.freebsd.org/Phabricator for details

May 25 2021, 4:13 PM · Linux Emulation, Core Team

May 24 2021

dchagin added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

hi, what is the purpose for this? it will be used read only. so what is the program depend on it?

May 24 2021, 6:46 AM · Linux Emulation, Core Team
emaste added a comment to D30378: linuxulator: Add filler for 'core' entry in linsysfs..

For future uploads please include full context by using e.g. git show -U99999 <hash> - see https://wiki.freebsd.org/Phabricator for details

May 24 2021, 1:38 AM · Linux Emulation, Core Team
lwhsu added a reviewer for D30378: linuxulator: Add filler for 'core' entry in linsysfs.: Linux Emulation.
May 24 2021, 1:14 AM · Linux Emulation, Core Team

May 23 2021

arrowd added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..
hostb0@pci0:0:0:0:      class=0x060000 rev=0x05 hdr=0x00 vendor=0x8086 device=0x5910 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = 'Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers'
    class      = bridge
    subclass   = HOST-PCI
pcib1@pci0:0:1:0:       class=0x060400 rev=0x05 hdr=0x01 vendor=0x8086 device=0x1901 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '6th-10th Gen Core Processor PCIe Controller (x16)'
    class      = bridge
    subclass   = PCI-PCI
vgapci1@pci0:0:2:0:     class=0x030000 rev=0x04 hdr=0x00 vendor=0x8086 device=0x591b subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = 'HD Graphics 630'
    class      = display
    subclass   = VGA
none0@pci0:0:8:0:       class=0x088000 rev=0x00 hdr=0x00 vendor=0x8086 device=0x1911 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = 'Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model'
    class      = base peripheral
xhci0@pci0:0:20:0:      class=0x0c0330 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa12f subvendor=0x1043 subdevice=0x201f
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family USB 3.0 xHCI Controller'
    class      = serial bus
    subclass   = USB
pchtherm0@pci0:0:20:2:  class=0x118000 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa131 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family Thermal Subsystem'
    class      = dasp
ig4iic0@pci0:0:21:0:    class=0x118000 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa160 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family Serial IO I2C Controller'
    class      = dasp
none1@pci0:0:22:0:      class=0x078000 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa13a subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family MEI Controller'
    class      = simple comms
ahci0@pci0:0:23:0:      class=0x010601 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa103 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = 'HM170/QM170 Chipset SATA Controller [AHCI Mode]'
    class      = mass storage
    subclass   = SATA
pcib2@pci0:0:28:0:      class=0x060400 rev=0xf1 hdr=0x01 vendor=0x8086 device=0xa112 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family PCI Express Root Port'
    class      = bridge
    subclass   = PCI-PCI
pcib3@pci0:0:28:3:      class=0x060400 rev=0xf1 hdr=0x01 vendor=0x8086 device=0xa113 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family PCI Express Root Port'
    class      = bridge
    subclass   = PCI-PCI
pcib4@pci0:0:28:6:      class=0x060400 rev=0xf1 hdr=0x01 vendor=0x8086 device=0xa116 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family PCI Express Root Port'
    class      = bridge
    subclass   = PCI-PCI
isab0@pci0:0:31:0:      class=0x060100 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa152 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = 'HM175 Chipset LPC/eSPI Controller'
    class      = bridge
    subclass   = PCI-ISA
none2@pci0:0:31:2:      class=0x058000 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa121 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family Power Management Controller'
    class      = memory
hdac0@pci0:0:31:3:      class=0x040380 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa171 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = 'CM238 HD Audio Controller'
    class      = multimedia
    subclass   = HDA
ichsmb0@pci0:0:31:4:    class=0x0c0500 rev=0x31 hdr=0x00 vendor=0x8086 device=0xa123 subvendor=0x1043 subdevice=0x15e0
    vendor     = 'Intel Corporation'
    device     = '100 Series/C230 Series Chipset Family SMBus'
    class      = serial bus
    subclass   = SMBus
vgapci0@pci0:1:0:0:     class=0x030200 rev=0xa1 hdr=0x00 vendor=0x10de device=0x1c8c subvendor=0x1043 subdevice=0x15e0
    vendor     = 'NVIDIA Corporation'
    device     = 'GP107M [GeForce GTX 1050 Ti Mobile]'
    class      = display
    subclass   = 3D
iwm0@pci0:2:0:0:        class=0x028000 rev=0x59 hdr=0x00 vendor=0x8086 device=0x095a subvendor=0x8086 subdevice=0x5010
    vendor     = 'Intel Corporation'
    device     = 'Wireless 7265'
    class      = network
re0@pci0:3:0:0: class=0x020000 rev=0x15 hdr=0x00 vendor=0x10ec device=0x8168 subvendor=0x1043 subdevice=0x200f
    vendor     = 'Realtek Semiconductor Co., Ltd.'
    device     = 'RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller'
    class      = network
    subclass   = ethernet
rtsx0@pci0:4:0:0:       class=0xff0000 rev=0x01 hdr=0x00 vendor=0x10ec device=0x5229 subvendor=0x1043 subdevice=0x202f
    vendor     = 'Realtek Semiconductor Co., Ltd.'
    device     = 'RTS5229 PCI Express Card Reader'
May 23 2021, 7:44 PM · Core Team
pitwuu_gmail.com added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

Give us the output of 'pciconf -lv' please.

May 23 2021, 6:25 PM · Core Team
arrowd added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

For my ASUS ROG GL553VE the following device hint fixed headset detection:

May 23 2021, 2:26 PM · Core Team

May 21 2021

pitwuu_gmail.com requested review of D30378: linuxulator: Add filler for 'core' entry in linsysfs..
May 21 2021, 12:01 PM · Linux Emulation, Core Team

May 20 2021

emaste added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

Do I have to do some specific action?

May 20 2021, 5:05 PM · Core Team
pitwuu_gmail.com added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

Please confirm Philippe Michaud-Boudreault <pitwuu@gmail.com> as the correct author info for Git.

May 20 2021, 9:36 AM · Core Team

May 19 2021

emaste added a comment to D30333: sound: add patch for Lenovo Legion 5 AMD..

Please confirm Philippe Michaud-Boudreault <pitwuu@gmail.com> as the correct author info for Git.

May 19 2021, 2:27 PM · Core Team
val_packett.cool added reviewers for D30333: sound: add patch for Lenovo Legion 5 AMD.: Contributor Reviews (src), avg, emaste.
May 19 2021, 10:15 AM · Core Team

May 18 2021

pitwuu_gmail.com requested review of D30333: sound: add patch for Lenovo Legion 5 AMD..
May 18 2021, 2:21 PM · Core Team

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Nov 25 2016

fabient closed D8130: Split arc4random mutexes to improve performance on IPSec traffic by committing rS309143: In a dual processor system (2*6 cores) during IPSec throughput tests,.
Nov 25 2016, 1:49 PM · Core Team

Nov 15 2016

delphij accepted D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Sorry for the delay (des@ have pinged me today). Consider this as a so@ approval as we haven't heard other objections so far.

Nov 15 2016, 6:07 PM · Core Team

Nov 9 2016

emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

delphij: is that OK for you?

Nov 9 2016, 10:41 AM · Core Team

Nov 7 2016

ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

By the second thought, no problem:) Since you mention that per-CPU locking is not your goal, in worst case the same harmless multiple stiring can happens since numruns belongs to the same arc4 data set to which stiring applied.

Nov 7 2016, 11:41 AM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Unfortunately this is a problem that is already present in the current version.

In current version it is not a problem (see my previous comment about multiple stiring above), but in case each arc4 instance can run on different arc4 data set, it can be a problem.

Nov 7 2016, 11:19 AM · Core Team
emeric.poupon_stormshield.eu updated the diff for D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Updated diff using full context, changed code according to delphij's comment

Nov 7 2016, 10:01 AM · Core Team
emeric.poupon_stormshield.eu added inline comments to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
Nov 7 2016, 9:57 AM · Core Team

Nov 4 2016

ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

unlocked read of arc4->numruns

Will lead to several arc4 stiring in worst case (which IMHO is non-practical case). Any number of stiring does not harm arc4, at least one stiring should be enough. But all this for one CPU case, I don't know about per-CPU locking in details so can't answer the next note.

Nov 4 2016, 10:05 PM · Core Team
delphij added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

I have some comments inline -- please fix the style change.

Nov 4 2016, 9:13 PM · Core Team

Oct 7 2016

ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Yes.

Oct 7 2016, 4:16 PM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Is that OK for you?

Oct 7 2016, 3:43 PM · Core Team
emeric.poupon_stormshield.eu updated the diff for D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Updated diff according to ache's remarks

Oct 7 2016, 8:11 AM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

This is nearly what I proposed before, but why would you reseed all the instances in case the user calls arc4rand with reseed = 1?

Because from current API point of view there is no separate CPU argument, so the call with reseed == 1 can come from any random CPU.
In general any random CPU may be not equal to unknown CPU for which this operation was made.

Oct 7 2016, 7:32 AM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
if (atomic_cmpset_int(&arc4rand_iniseed_state, ARC4_ENTR_HAVE, ARC4_ENTR_SEED) ||
    reseed) {
        ARC4_FOREACH(arc4)
                arc4_randomstir(arc4);
}
...
if (arc4->numruns > ARC4_RESEED_BYTES || 
    tv.tv_sec > arc4->t_reseed)
        arc4_randomstir(arc4);

This is nearly what I proposed before, but why would you reseed all the instances in case the user calls arc4rand with reseed = 1?

Oct 7 2016, 7:21 AM · Core Team

Oct 6 2016

ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Not sure this is a big security concern or not?

Maybe I am wrong, but I don't see big deal here - the moment of good randomness available is unpredictable in the time intervals we consider, and if some threads got it a bit later (on the next call), I don't see the problem.

Oct 6 2016, 4:49 PM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
In D8130#169388, @ache wrote:

There can be small window when arc4rand_iniseed_state is already set to SEED, but arc4_randomstir() is not called yet. And right in this time another thread calls the code. Well, we miss only single reinitialization per-CPU (more are time-consuming and can't fit between the check and immediate function call), on the next call they will be already reinitialized. Dou mean another scenario?

Yes that is what I meant. Not sure this is a big security concern or not?

Oct 6 2016, 4:13 PM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
In D8130#169387, @ache wrote:

The problem is that another thread may call the arc4rand() function and get some unsafe random bytes before the stir actually occurs and after the state was set to SEED.

Please show how it can happen in steps by steps. In old code if the state was SEED, it surely reinitialized, and reinitialization itself keeps a lock, so RNG can't move further and wait for reinitialization (from any thread).

Oct 6 2016, 4:10 PM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

There can be small window when arc4rand_iniseed_state is already set to SEED, but arc4_randomstir() is not called yet. And right in this time another thread calls the code. Well, we miss only single reinitialization per-CPU (more are time-consuming and can't fit between the check and immediate function call), on the next call they will be already reinitialized. Dou mean another scenario?
We can move both check and function call under lock, but it will slow things down, i.e. the thing you fight against.

Oct 6 2016, 3:19 PM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

The problem is that another thread may call the arc4rand() function and get some unsafe random bytes before the stir actually occurs and after the state was set to SEED.

Please show how it can happen in steps by steps. In old code if the state was SEED, it surely reinitialized, and reinitialization itself keeps a lock, so RNG can't move further and wait for reinitialization (from any thread).

Here is what I propose:

In your code 'reseed' variable should be move to the same 'if' as 'arc4rand_iniseed_state' placed, we never know what we cpu we reseed otherwise.
The next thing I don't like much is possible double initialization, if this condition additionaly meet in the same time 'if ((arc4->numruns > ARC4_RESEED_BYTES) || (tv.tv_sec > arc4->t_reseed))
All you need is simple local 'reseedall' variable and set it where ARC4_FOREACH(arc4) is.

Oct 6 2016, 2:59 PM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
In D8130#169376, @ache wrote:

I meant the arc4rand_iniseed_state variable.

I too. Without locking or atomic either yet one additional seeding can happens or no seeding can happens at all (CPU writing to another half of word, which is already checked).

I do agree with that, but on the very first call of arc4rand(), we can make sure readomstir() is called,

Not all stiring are equal) Non random stiring is done to just not block arc4 on early boot phase.
When good randomnes becomes available (which arc4rand_iniseed_state indicates) it must be reinitialized immediately on the next call.

Oct 6 2016, 12:11 PM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

I meant the arc4rand_iniseed_state variable.

I too. Without locking or atomic either yet one additional seeding can happens or no seeding can happens at all (CPU writing to another half of word, which is already checked).

I do agree with that, but on the very first call of arc4rand(), we can make sure readomstir() is called,

Not all stiring are equal) Non random stiring is done to just not block arc4 on early boot phase.
When good randomnes becomes available (which arc4rand_iniseed_state indicates) it must be reinitialized immediately on the next call.

Oct 6 2016, 11:04 AM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
In D8130#169374, @ache wrote:

But I am not sure to see the actual benefit of this atomic?

It allows to not play with locking.

I meant the arc4rand_iniseed_state variable.

Oct 6 2016, 10:47 AM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

But I am not sure to see the actual benefit of this atomic?

It allows to not play with locking.

I guess the read_random() call is blocking until the underlying entropy processor becomes secure?

Yes. Then it allows arc4 reseed. There is no point to reseed it before it happens with non random data.

Oct 6 2016, 10:38 AM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

That's a good point indeed.

Oct 6 2016, 10:28 AM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

reseed arg without specifying particular CPU means nothing but stir all CPUs too. And specifying that CPU is impossible on API level - nobody know from which CPU this code will be called.

Oct 6 2016, 9:32 AM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

The problem is that arc4rand_iniseed_state which is reset on the first use with atomic currently asssume that all RNGs are stired, but really only first one.

Oct 6 2016, 9:25 AM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Do you have other remarks on this patch?

Oct 6 2016, 9:13 AM · Core Team

Oct 5 2016

emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Thanks for working on this, but I have some different ideas which I don't really have the time to sit down and implement at this time that I feel like sharing and may be useful:

I think we could take a different approach: now that we have the pseudo-random state per-CPU, perhaps we can make them CPU-bound and completely eliminate the locks and use critical sections instead?

Oct 5 2016, 7:07 AM · Core Team

Oct 4 2016

delphij added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Thanks for working on this, but I have some different ideas which I don't really have the time to sit down and implement at this time that I feel like sharing and may be useful:

Oct 4 2016, 4:18 PM · Core Team
emeric.poupon_stormshield.eu updated the diff for D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Changed malloc test to KASSERT

Oct 4 2016, 1:29 PM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
In D8130#168678, @ache wrote:

Sorry, my prev. comment was sent non-edited. Please forget it if you got it through the mail and re-read here instead.

No problem!
Since the call is very unlikely to fail, what about a KASSERT on failure then? That seems to be an acceptable compromise.

Oct 4 2016, 9:39 AM · Core Team
emeric.poupon_stormshield.eu added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
In D8130#168678, @ache wrote:

Sorry, my prev. comment was sent non-edited. Please forget it if you got it through the mail and re-read here instead.

Oct 4 2016, 8:47 AM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.

Sorry, my prev. comment was sent non-edited. Please forget it if you got it through the mail and re-read here instead.

Oct 4 2016, 8:29 AM · Core Team
markm added a reviewer for D8130: Split arc4random mutexes to improve performance on IPSec traffic: delphij.

Add SO

Oct 4 2016, 8:17 AM · Core Team
ache added a comment to D8130: Split arc4random mutexes to improve performance on IPSec traffic.
In D8130#168667, @ache wrote:

It will be better to use non-failing malloc flag. arc4_init() can't fail.

You mean a M_WAITOK flag? I was wondering: are you sure it is really safe to sleep in this context?

Oct 4 2016, 8:14 AM · Core Team