Add a driver for NXP LS1088a clockgen support which passes
configuration information to QorIQ clockgen class.
The implementaiton started off from a copy of ls1028 support and was
adjusted accordingly.
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I found one minor issue. Even though it's under HWACCEL3 ifdef, I think it should be fixed.
| sys/arm64/qoriq/clk/ls1088a_clkgen.c | ||
|---|---|---|
| 169–176 | According to the doc, Cluster PLL2 divide-by-2 is selected when the value in HWA3CSR is equal to 6, not 2, so ls1088a_cga_pll2_div2 should be placed at ls1088a_hwaccel3_parent_names[6]. I think that ls1088a_cga_pll2_div3 should be the next element in the array. I am not 100% sure though, as it seems that there is an error in the document itself (both divide-by-2 and divide-by-3 are selected by 0110 according to the doc and that's impossible) | |
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Fix ls1088a_hwaccel3_parent_names using the correct offsets
in the array for pll2_div[23] as pointed out by dgr.
| sys/arm64/qoriq/clk/ls1088a_clkgen.c | ||
|---|---|---|
| 169–176 | I see the same in my version for pll[12]_div2 and pll[12]_div3 for HWA[123]CSR in 4.4.2.4 Fields. And Reserved starting at 111 rather than at 1000. | |
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How is '#ifdef HWACCEL3' compatible with the generic kernel and why do we need it at all?
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It's simply there to disable the code for now; while it's in the spec, I could not see anything using it. I can spell it `#ifdef __notyet__` if you prefer that.
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And why didn't you leave it enabled? IMHO all HWACCEL blocks look the same, so the risk of a possible error is minimal.