I looks like some lines might be wider than 80 characters

Is this something cheri could use too?

It looks like a few lines passed 80 characters so will need to be split.

We should name __hypctx_vncr_sysreg to __hypctx_vncr_sysreg_64 or similar to indicate it supports 64-bit registers (and the other accessors). CHERI could add a version to indicate it handles capabiliries (or it handles pointer-like registers).

Use D57017 to build the instructions

• Remove the unneeded bind handler
• Cleanup better on attach failure

• Clean up table size/alignment handling
• Read the table PA range from the register
• Support 2 level device tables
• Support a non-coherent ITS
• Cleanup better on attach failure
• Implement more functions

• Clean up table size/alignment handling
• Read the table PA range from the register
• Handle IPIs without having to change common code

This can be closed? It's been merged into th re-opened D55492

Just style

In D56551#1295942, @jrtc27 wrote:

In D56551#1295771, @andrew wrote:

It looks like the two capability registers this change affects are elr_el1 and vbar_el1. Both of these have at least 128 bits of space before the next register, so storage shouldn't be a problem for Morello.

sp_el0, tpidr_el0, tpidrro_el0, and tpidr_el1 could be split into a new capability array when they are managed in a later change.

Also sp_el1 and tpidr_el2 in the VNCR space (why is tpidr_el2 even in there? I don't know if I want to know...). I would really like to not land this patch before it's clear there's an *easy* path to making this work on Morello. Breaking bhyve on Morello would be really quite unfortunate and hostile towards CheriBSD.

It looks like the two capability registers this change affects are elr_el1 and vbar_el1. Both of these have at least 128 bits of space before the next register, so storage shouldn't be a problem for Morello.

I think we can split out the pmap and busdma parts into 2 new revisions (i.e. one for pmap, one for busdma)

In D56518#1295709, @alc wrote:

Just out of curiosity, where are the pmap changes?

We will need to handle accessing different sized registers to support FEAT_D128, e.g. VTTBR_EL2 will be 128 bit there.

I can move them to something like 200/201. I think the Arm Permission Overlay Extension (FEAT_S1POE) could then reuse SEGV_PKUERR as it is similar.

Stop switching sctlr user bits for kernel threads

Was it decided if this was an acceptable approach? I found the sanitizer runtimes also need this to work correctly, so would like to push to fix them

Does anyone have any more testing they would like to do, or shall I push this to main?

Change the SEGV_MTE* values

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