My initial tests did not show any problems, but I only checked some basic functions of the server, for example CGI was not tested. This server is quite minimal, so testing reasonable part of this should not take long. Hopefully, the maintainer will tell us more about that. If not, I'll setup something and test this myself. Disabling PIE entirely, just because it does not build, may be an overkill here.

It seems that the maintainer doesn't have an account here. I'll send an email directly.

I have looked at *.mk files and if I am not mistaken it seems that there is currently no clean way of having a separate default option for PIE for base, as the __DEFAULT_YES_OPTIONS from bsd.opts.mk takes precedence and moving this option from bsd.opts.mk will leave us with no MK_PIE defined.

Added a comment indicating that PIE is incompatible with -mno-abicalls. Thanks, @emaste.

In D27025#603548, @lwhsu wrote:

Does it make sense also report to the upstream? https://github.com/jemalloc/jemalloc

Replace SOC_NXP_LS1046 with SOC_NXP_LS.

Replace SOC_NXP_LS1046A with SOC_NXP_LS.

Add ls1046_gpio device in kernel config. Replace SOC_NXP_LS1046 with SOC_NXP_LS.

Replace SOC_NXP_LS1046 with SOC_NXP_LS.

Added comment about 1:1 sysclk and coreclk divider nodes.

I'll change it in all the patches to SOC_NXP_LS.

Modified to work with new version of D24351

Modified driver to use clock id for lookup instead of names.
Modified the way sysclk and coreclk are created - currently
should follow bindings. The clock sources for PLLs are now
selected by driver automatically depending on the presence
of coreclk.

Moved to dev/iicbus/rtc/ directory.

Moved to dev/iicbus/gpio directory.

Hi, if you have any more comments or remarks, please let me know. Thanks.

Hi, if you have any more comments or remarks, please let me know. Thanks.

Hi, if you have any more comments or remarks, please let me know. Thanks.

Hi, if you have any more comments or remarks, please let me know. Thanks.

Hi, if you have any more comments or remarks, please let me know. Thanks.

Hi, if you have any more comments or remarks, please let me know. Thanks.

Hi, if you have any more comments or remarks, please let me know. Thanks.

Added pin_access_32 and pin_config_32 functions.
Changed get_name function to generate "pin <pin_number>" as name.
Additional minor fixes.

Added vf_i2c as driver name in files.arm64

Removed "All rights reserved" from copyright notice.
Added clock enabling in attach function.

Each PLL has multiple dividers. For each PLL single PLL node is created
and fixed factor clock nodes are created for each divider that the PLL has.
So only a single PLL node exists, but there are multiple divider nodes.

Thanks, I'll prepare patch in the coming days.

The controller is actually connected to platform PLL, which
is always enabled, but since the controller might be used in
different SoC in the future, I'll add clock enabling.

In D24466#538161, @manu wrote:

Do you know how different this controller is compared to the other fsl ahci controller ? (like ls208x etc ...)
If it's very different the file should be renamed.

Add dependency on SOC_NXP_LS1046A option.

Renamed file to rx8803.

Removed code that needed interrupts to start before executing.

The problem was with dts file not conforming to device tree documentation. Abandoning.

Added bus_release_resources call and dependency on SOC_NXP_LS1046A.

Added SOC_NXP_LS1046A dependency.

I modified the driver to use the modified QorIQ clockgen classes.
Also added dependency on SOC_NXP_LS104A.

Pretty much a total rewrite. Now more closely represents the clock
node structure. For PLL nodes separate classes are now used, but
the PLL registers are read only, so there is no write functionality.
Other than that multiplexers are now represented by built-in classes
and PLL dividers are represented by fixed factor clocks.

Thanks for the comments, in the coming days I'll prepare v2 of this diff.