- User Since
- Feb 3 2015, 4:54 AM (201 w, 3 d)
Sun, Dec 9
Imho, aggregated reading of ID registers is not a best solution.
Personally, I think that we should implement aggregated view by using HWCAPS (As we must do this in any case, upcoming COMPAT32 simply expects this).
But we should return actual/real values of ID registers. This allow us to write program which iterates over clusters and selects best cores for given workload.
I mainly talking about SHA or SVE extensions here.
Sat, Dec 8
Fri, Dec 7
Wed, Dec 5
bingo! I'm on r341345. And yes, r341347 fixed it.
Thanks and sorry for noise.
Tue, Dec 4
Ahh, right, I overlooked this, sorry. So I taking back WITHOUT_CAPSICUM case.
How this can works on kernels build without 'options CAPABILITIES'? Note that CAPABILITIES option is
not included in kernel option for small embedded boards (arm, mips...)?
We should change CAPSICUM to mandatory or implement fallback here (as we already do in rest of tree)
Mon, Dec 3
Sun, Dec 2
Only kernel was changed during bisecting, nothing else. And all kernels was cross-compiled by
same toolchain. Kernel before r339819 works, r339819 hangs, and fresh current with r339819
reverted also works. Also, during bisecting, any kernel after r339819 hangs.
So I thing that r339819 is culprit.
Unfortunately, this patch destabilized arm kernel.
The bad thing is that my Tegra does not panic, just hangs hard and I can’t even enter the JTAG debugger .
Moreover, this issue is very rare, I can do finish full buildkernel in most cases. The only known testcase is full
build of qt5-webengine (~16k of C++ files, +10 hours of compilation time).
Thu, Nov 15
Nov 3 2018
Oct 30 2018
can you, please, subclass phy to USB specialized variant (say phyusb or usbphy)? You can use clk (clkdiv, clkmux ...) as template. We should implement lots of USB OTG related function here. VBUS voltage and over-current detection, ID pin status change interrupt, OTG state machine and I thing that should use proper layering from beginning.
If you too busy for this, I can implement (empty) subclass in next 2-3 days.
Aug 25 2018
Aug 22 2018
Firstly, I want to say that this patch is OK. It only slightly changed memory layout for TLS segment (because it uses malloc_aligned()) which exposed unrelated bug in ARM TLS relocation.
Aug 13 2018
Aug 8 2018
Output mailed directly.
And about linker - it's hard to say :)
Tested on Jetson TK1 (cortex-A15) without single problem.
From preliminary collected statistic it looks like pmap_enter(..., psind == 1) is used ~60 times per buildworld.
Unfortunately, the same statistic also told me that is pmap_enter_object() doesn't not create single 1MB mappings, even for shared libraries.
I'm pretty sure that this worked before - but this regression is not related to this patch.
Aug 1 2018
The commit message is a bit misleading. This patch ensures DMA coherency only for control structures but audio data buffers are not covered by required bus_dmamap_sync() operations. (We simply don't have right sync operation for syncing in progress DMA buffers - something like make buffer range snapshot before CPU read and make buffer range snapshot after CPU write).
Can you, please, elaborate this fact in commit message.
Jul 29 2018
Applied, booted new kernel and make buildworld passed without problem.
Thanks for your ARM effort.
Jun 16 2018
Rebased to current, renamed UBOOT_BOOT_API to LINUX_BOOT_API
Mar 9 2018
Mar 2 2018
Tested also on RPi-B (armv6) without problem.
Please, also remove rng related lines from sys/dts/arm/rpi.dts stubs.
Feb 10 2018
+100 for overlays.
But I'm not sure if it's right time to publish base .dtb files in this way. We cannot use it for now (because interrupts for uart and spi are routed throw "bcm2835-aux") and it's unclear if binding headers (dts/include/dt-bindings/*) are same (or compatible) as linux mainstream ones.
Jan 19 2018
- print actual mitigation variant if bootversode
- slightly restructure code to make additional vendors or CPUs addition easier
Jan 18 2018
Addressed all objections.
Jan 17 2018
Jan 16 2018
Jan 12 2018
mkimage, imho, is not supported(or not preferred - it have bundled load address inside) on arm64, but this is not important yet.
I agree but, unfortunately, yes. The context_id is used for selecting right stack. See line 270 in new file.
Boot CPU have always cpuid 0 so yes, it boots (i hope). I have disordered cpus nodes in my DTS and all looks OK.
Jan 11 2018
Yep, I known. But my actual situation with Jetson TX1 board is more complicated.
- the TX1 firmware can only load U-Boot for eMMC.
- shipped U-Boot doesn't support EFI
- on OS start, U-Boot modifies DTB (it excludes memory used by secure monitor and PSCI,, it modifies the pinmux table so that it matches the current setting), it stored trained settings for DDR4 controller for various memory frequencies...)
Dec 26 2017
imho, we should put platform specialized drivers to dev subtree only if given driver can be reused on multiple platforms. I personally vote for not moving it.
Dec 23 2017
Dec 21 2017
Everything else looks OK for me.
Nice, this looks OK for me
But,it seems that there are some related problems:
- the PCB for proc0/thread0 is allocated on top of stack, from dirty memory, but not all fields are not initialized - this is probably a root cause why this bug is not visible on all boards.
- we leaks initial low memory mappings in kernel_pmap. This can results to double mappings with different attributes which is undefined behavior. Imho, we should clear all mappings in low memory region.
Dec 19 2017
yes, but the fix looks incorrect for me.
I think that we can have same problem with secondary cores(idle threads). Imho, cpu_startup() is more appropriate place for this and we should derive TTBR0 value from kernel_pmap. See arm version of cpu_startup() and call to pmap_set_pcb_pagedir(kernel_pmap, pcb); .
No objection from arm or intrng side.
I can confirm same issue on Cortex-A72. Loading zero to TTBR0_EL1 causes immediate exception (in sched_switch+0x3a0).
Dec 12 2017
Dec 8 2017
thanks. I will incorporate all your comments into final commit.
Dec 5 2017
Nov 29 2017
Sorry for delay. We don't support arm for FreeBSD 10 and arm packages are built only for FreeBSD11 and higher.
Nov 25 2017
Generally speaking, I think that implementing more and more knowledge about TLS ABI into kernel is direct way to hell and it simply leads to hard to solve compatibility issues.
The ideal kernel should take TP pointer as opaque value, without any attempt to interpret it.
Nov 20 2017
with full respect, I don’t think that this is right way. Moreover, I think that you papering over real problem there.
With this patch, what’s happen if someone requests any higher alignment (that actual 16) for TLS data? Or, can patched kernel run the old init (pre r324938)?
Nov 19 2017
I can confirm that R cad be built on native ARMv7 system with this.
Nov 3 2017
Seems that exp-run passed without problems. Can you, please, commit this ?
Nov 2 2017
- malloc_aligned() modified to rtld version
- added alignment fix also for Variant I
- check malloc() return values
- use custom version of assert()
Oct 30 2017
Oct 20 2017
Imho yes, AT_ values are defined in machine/elf.h so user should include it in (almost) all cases.
Would be nice to provide some kind of man page.
I will ask Ian for man page, this kind of job is significantly out of my skill (even in my native language). My bad I known.
Split out libc changes
Oct 18 2017
Drop getauxval(), make _elf_aux_info() public.
My exp-run for selected ports just ended and It found unexpected problem.
Some ports detect getauxval() presence and if is present then expect that all (linux specific) AT_ flags are defined and implemented (e.g. security/p11-kit ).
Oct 17 2017
Sep 10 2017
Sep 9 2017
Sep 8 2017
Can be this MFCed to stable? In other words, do we support in place upgrade from 10 (soft FP ABI) to 11 (hard FP ABI)?
From my point of view, this is OK for FBSD 12.
Sep 6 2017
Aug 11 2017
Aug 4 2017
Jun 28 2017
Jun 21 2017
Jun 18 2017
Jun 17 2017
Oups, my bad, sorry.
We cannot use standard way for tunable sysctl initialization here. SYSINIT machinery is executed far after cpuinfo_init() so boot CPU doesn't get right quirks.
Anyway, I submitted fix for this in r320054.
So again, sorry for troubles...
I'm fine with rest.
Jun 15 2017
I'm fine with both solutions, with preference to "arm,io-coherent". Using standardized, documented way is always better :)
I do not think this patch was accepted in mainline Linux -> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-August/363953.html
When a PL310 cache is used in a system that provides hardware
coherency, the entire outer cache operations are useless, and can be
This is significantly incorrect/misleading/false sentence. All these outer cache operations are necessary for standard mapping operations, irrespective of coherency status.
Please, reword this part in commit.