arm64/vmm: Implement vgic_v5

[sarah.walker2_arm.com]

Summary

Adds support for GICv5 as both a host and guest. Additionally, on platforms with
FEAT_GICE_LEGACY, supports a GICv3 guest under a GICv5 host.

The current implementation only implements the IRS component. The ITS is not
currently emulated, which prevents the use of MSIs.

Co-developed-by: Andrew Turner <[e-mail]>
Sponsored by: Arm Ltd

[sarah.walker2_arm.com]

Rebase; fixed one conflict

[andrew]

I think we also need to handle IRS_IIDR and IRS_PE_*.

sys/arm64/vmm/io/vgic.c

180

Unneeded

sys/arm64/vmm/io/vgic_internal.h

101

Unneeded

118

Do we need any per-CPU data for GICv5? If not this can change to say so

sys/arm64/vmm/io/vgic_v5.c

31

Not needed as later headers include it. It was previously needed for the __FBSDID macro, but that has been removed from .c files.

93–94

Should this use the sanitised register value?

121–126

We should create macros for these

129

And this

173

Do we have a macro for this?

183

We can remove some of these, they were there so I could check which registers have been implemented

243

It would be useful to add a comment here explaining why registers are unimplemented, e.g. is RAZ/WI because IRS_IDR0.VIRT == 0

393

Don't we need LPIs for IPIs? It looks like Linux checks for it.

452

Should we check IRS_IST_BASER.VALID != 1 first? If it's valid then this is read-only

552

We should only write when IRS_IST_BASER.Valid != 1

697–698

And the same for SPI

703

You could move GICV5_PPIS_PER_REG and GICV5_PPI_COUNT to a header & use them here

735

Do we need this panic?

751

This should return an error

sys/arm64/vmm/vmm_hyp.c

961

Is there a reason to put this here & not in a vgic specific function?

[sarah.walker2_arm.com]

Address review comments.
Fix maintenance IRQ in GICv5 legacy mode.
Correct ID_AA64PFR0 and ID_AA64PFR2 values.
Implement IRS_AIDR register.
Disable trapping of GIC CDRCFG instruction.

[sarah.walker2_arm.com]

Rebase