Fix indentation

Fix indentation

Fix indentation

Fix indentation

Fix indentation

Fix indentation

Fix indentation

Fix indentation

Fix indentation

Fix indentation

Fix indentation

Fix indentation

Use genassym for assembly offsets

Address review comments

Address review comments

Address review comments

Address review comments

Address review comments

Address review comments

Correct nVHE omission

Correct nVHE omission

Correct nVHE omission

Correct nVHE omission

Use Static_assert to ensure correct struct hypctx size

Use Static_assert to ensure correct struct hypctx size

Use Static_assert to ensure correct struct hypctx size

Use Static_assert to ensure correct struct hypctx size

Use Static_assert to ensure correct struct hypctx size

Use Static_assert to ensure correct struct hypctx size

Correct register name

I think this should be all outstanding issues sorted out now. To adapt this to CHERI you could do something as simple as:

Address remaining style review comments

Address remaining style review comments

Address remaining style review comments

Address remaining style review comments

Address remaining style review comments

Address remaining style review comments

Use char* for ptr arithmetic

Use char* for ptr arithmetic

Use char* for ptr arithmetic

Use char* for ptr arithmetic

Use char* for ptr arithmetic

Use char* for ptr arithmetic

Then why are some places using *hypctx_sys_reg directly and mutating it?

Fix omission

Fix omission

Fix omission

Fix omission

As in we'd change the definition of the hypctx_sysreg enum itself? And then do "something" to special case it in the function? And have a new hypctx_sys_reg_cap that returned uintcap_t *? That seems like it could work. Though I've tagged @markj on this review as he did the initial adaptation of the proposed bhyve/arm64 code to Morello.

I would really like to not land this patch before it's clear there's an *easy* path to making this work on Morello.

Ah thanks, that's good to know! I'm new to all things BSD, always nice to get some additional context :)

In D56551#1295942, @jrtc27 wrote:

In D56551#1295771, @andrew wrote:

It looks like the two capability registers this change affects are elr_el1 and vbar_el1. Both of these have at least 128 bits of space before the next register, so storage shouldn't be a problem for Morello.

sp_el0, tpidr_el0, tpidrro_el0, and tpidr_el1 could be split into a new capability array when they are managed in a later change.

Also sp_el1 and tpidr_el2 in the VNCR space (why is tpidr_el2 even in there? I don't know if I want to know...). I would really like to not land this patch before it's clear there's an *easy* path to making this work on Morello. Breaking bhyve on Morello would be really quite unfortunate and hostile towards CheriBSD.

Fix non-VHE omission

Fix non-VHE omission

Fix non-VHE omission

Fix non-VHE omission

Fix non-VHE omission

Fix non-VHE omission

Handle non-VHE, store the vncr page as a pointer

Handle non-VHE, store the vncr page as a pointer

Handle non-VHE, store the vncr page as a pointer

Handle non-VHE, store the vncr page as a pointer

Handle non-VHE, store the vncr page as a pointer

Handle non-VHE, store the vncr page as a pointer

In D56551#1294533, @andrew wrote:

We will need to handle accessing different sized registers to support FEAT_D128, e.g. VTTBR_EL2 will be 128 bit there.

Encode VNCR values into enum hypctx_sysreg as 64-bit offsets

Encode VNCR values into enum hypctx_sysreg as 64-bit offsets

Encode VNCR values into enum hypctx_sysreg as 64-bit offsets

Encode VNCR values into enum hypctx_sysreg as 64-bit offsets

Encode VNCR values into enum hypctx_sysreg as 64-bit offsets

Encode VNCR values into enum hypctx_sysreg as 64-bit offsets

Update

Update

Update with changes to other commits in the stack

Update

Update with changes to other commits in the stack

Merge hypctx & VNCR into one allocation, adjust pointer type

Update register indentation

Yes, exactly. This loses all type system flexibility. At least if you just made a struct that matched the VNCR layout we could change the types, and ok it wouldn't then match, but that wouldn't matter for our use case (and if a CHERI + Arm + nested virt system ever exists then the layout can be made to match that). Whereas now we'd have to go and meticulously tweak all the magic VNCR constants to give us a layout that works, and tweak the one-function-to-rule-them-all to be two functions, one for integers and one for capabilities, since we have multiple types.

In D56551#1294463, @jrtc27 wrote:

This is really quite an obnoxious change to deal with for Morello, where some of these registers are 128-bit capabilities not 64-bit integers...

Fix commit description