The IRPERF MSR counter (0xc00000e9) exposes an instructions-retired count
when read. Its support is advertised through CPUID leaf 0x80000008 EBX bit 1.
If this bit is set, the CPU supports the IRPERF MSR. For it to be used
by the system, bit 30 of the HWCR MSR (0xC0010015) needs to be enabled.

This patch checks for availability of the feature and enables the bit. If
the feature is available, the hwpmc PERF class detects its presence and
registers a third PERF MSR counter that allows hwpmc users to measure
instructions retired using IRPERF. This is AMD-only, as Intel does not
support IRPERF.

Due to erratum #1054 affecting AMD Zen 1 before model 30h, IRPERF is only
enabled for AMD Zen 1 model 30h onwards and later microarchitectures. This
commit also implements a validation step to make sure the IRPERF counter
is actually incrementing; otherwise, the feature is not enabled. This
guarantees it is working as expected before being made available to the
system and users.

To support this, the perf_pmcdesc[] structure changed from being
statically initialized with 2 entries (MPERF/APERF) to being populated
dynamically. If both MPERF/APERF and IRPERF are supported, the structure
will contain three entries: MPERF, APERF, and IRPERF. Each entry now also
carries its own MSR address and PMC event, so perf_read_pmc() reads the
MSR to use from the matching perf_pmcdesc[] entry at runtime instead of
switching over a fixed set of row indices.

Definitions for the features available on the HWCR MSR did not previously
exist. This commit adds macros for those features, including
HWCR_IRPERFEN. The MSR definition for MSR_IRPERF was also missing and has
now been added.

This commit also updates the manual page accordingly.

Signed-off-by: Anderson Nascimento <anascime@amd.com>
Sponsored by: AMD