♟ mhorne

tarfs.4: update title after move to section four

Complete the change by removing the content from the developers-handbook.

Nice. The flag acts as a meaningful annotation, regardless of any effects on fragmentation.

In D45981#1048758, @jhb wrote:

I'd kind of wanted to kill MPASS eventually since I have used it for all sorts of assertions that have nothing to do with SMP, and other assertions in the language permit 1 argument variants (assert() and static_assert()). However, it is simpler to not have the single arg version and it does mean _KASSERT_MACRO would be temporary. We could always add a single arg variant later if we wanted.

Status/2024q2/riscv.adoc: Add report

time.1: minor cleanup (alignment/macro/spdx)

plic: add thead,c900-plic compatible

amd64: use pc_is_full() helper function

riscv: fix pv_chunk check in pmap_pv_demote_l2()

riscv: Don't need to check the return value with NULL

arm64: simplify physmap usage in pmap_bootstrap()

busdma: avoid buflen underflow

riscv: include PV chunks in kernel dump

riscv: support PV_STATS pmap option

In D45761#1044584, @alc wrote:

In D45761#1044534, @markj wrote:

I was about to comment that other pmaps still use atomics for these counters, but it seems that amd64's also been using counter(9) for a while. I'm a bit skeptical that that's really necessary (except perhaps for p_failures), but it doesn't have much downside either. It would be nice to make at least arm64 consistent.

I share your skepticism for the L2 counters, but I see no real harm in this change. Similarly, I would have no objections to making the same change on arm64. On arm64, we are using counter(9) for 64KB pages, where the counts are typically two orders of magnitude larger.

wpa_cli.8: describe better + tag spdx + linter nit

if_genet: don't load DMA mapping when tx_queue is full

riscv: remove a redundant check on PGA_WRITEABLE

Rebase after 32d2a1de3d64.

arm64: correct physmap bounds in pmap_bootstrap()

Update according to C910 specification.

Flesh out the missing stat calls.

riscv: adjust physmem reservation

rk_pinctrl: fix error check

if_genet: don't load DMA mapping when tx_queue is full

wpa_cli.8: describe better + tag spdx + linter nit

ofw: convert boolean_t to bool

I could apply the same guard to bounce_bus_dmamap_load_phys() methods, but in those functions it is easier to see that underflow is not possible, so I haven't yet.

The new .S file needs a license.

Thanks for this. One tweak required.

Apply memattr bits to mappings created at the end of pmap_bootstrap() (this was missed).

Handle feedback; mainly, update the assertions.

Hi, just a preliminary look, much of the vmm code is beyond me. I hope to test this stuff in a couple weeks!

build.7: +freebsd to description, link development

build.7: update cross-compile example

build.7: nit section order, tag spdx

git-arc.1: list width typo

riscv: drop l1pt argument from pmap_bootstrap()

riscv: smarter DMAP construction

riscv: rework page table bootstrap

riscv: Construct an identity map in locore.S

Finish implementation of pmap_change_attr_locked().

riscv: improve commentary around initial stvec

riscv: Don't handle missing kernel L3 pages

riscv: adjust physmem reservation

Drop unneeded warning print.

Handle comment from markj.

rk_pinctrl: fix error check

There is actually more to be done here...

Adjust comments referencing vm_mem_init()

arm64, riscv: removed unused struct pv_addr

arm64, riscv: remove unused declaration

ieee80211_vap(9): fix the title

In D43251#1038334, @aokblast wrote:

Just a question, how you test on kernel, I use spike --kernel /path/to/kernel /path/to/sbi. It give me invalid address error even after I add -m0x1000000,0x2000.

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