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[DRAFT/RFC] riscv: T-HEAD PBMT support
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Authored by mhorne on Jun 3 2024, 6:51 PM.
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Details

Reviewers
markj
br
jrtc27
jhb
Group Reviewers
riscv
Summary

T-HEAD CPUs provide a spec-violating implementation of page-based memory
types, using PTE bits [63:59]. Aside from the philosophical problems
with this approach, the reality of increasing availability of T-HEAD
platforms which implement this means that we need to consider adapting
to this.

Add support for this "errata". There is still quite a bit of refinement
needed, as well as testing. Note that this change is not enough on its
own, but some workaround will be needed for the bootstrap (locore) page
tables as well.

Diff Detail

Repository
rG FreeBSD src repository
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Build Status
Buildable 58379
Build 55267: arc lint + arc unit

Event Timeline

mhorne requested review of this revision.Jun 3 2024, 6:51 PM
sys/riscv/include/pte.h
111–114

Is there no attribute for cacheable RAM, or should one of the labels here (PMA) use cacheable in the description?

sys/riscv/riscv/pmap.c
4890

If you pull memattr_mask down into the prior commit, I think you can just use it directly in this function instead of the local mask temporary?

Update according to C910 specification.

Tested on hardware (Allwinner D1), with workarounds applied, which boots until
late device probing.

sys/riscv/include/pte.h
126–129

For some reason I was getting strange (incorrect) bitmasks with the previous version. This is not final but it works...

sys/riscv/riscv/pmap.c
4890

Eventually, this function might be expanded to support changing the page protection bits as well, see pmap_change_props_locked() on amd64. In this case mask and bits will apply to more than the memory attributes. Therefore I think it is fine to leave it as is.