riscv: T-HEAD PBMT support

[mhorne]

Summary

T-HEAD CPUs provide a spec-violating implementation of page-based memory
types, using PTE bits [63:59]. Add basic support for this "errata",
referred to in some places as an "extension".

Note that this change is not enough on its own, but a workaround is
needed for the bootstrap (locore) page tables as well.

[jhb]

sys/riscv/include/pte.h

111–114

Is there no attribute for cacheable RAM, or should one of the labels here (PMA) use cacheable in the description?

sys/riscv/riscv/pmap.c

4771

If you pull memattr_mask down into the prior commit, I think you can just use it directly in this function instead of the local mask temporary?

[mhorne]

Update according to C910 specification.

Tested on hardware (Allwinner D1), with workarounds applied, which boots until
late device probing.

[mhorne]

sys/riscv/include/pte.h

126–129

For some reason I was getting strange (incorrect) bitmasks with the previous version. This is not final but it works...

sys/riscv/riscv/pmap.c

4771

Eventually, this function might be expanded to support changing the page protection bits as well, see pmap_change_props_locked() on amd64. In this case mask and bits will apply to more than the memory attributes. Therefore I think it is fine to leave it as is.

[mhorne]

Regenerate now that the series is more complete.

[mhorne]

sys/riscv/include/pte.h

111–114

I think this was a typo. Fixed now.