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Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC

Assert that hart < MAXCPU
Rename cpu variable to hart

Fix bug: use CPU_FILL to fill up kernel pmap pm_active.
all_harts is not initialized yet in pmap_boostrap()

Use all_harts mask in release_aps()

Store hart in struct pcpu
Store harts not CPUIDs in pmap->pm_active

RISC-V ISA does not specify how to manage physical memory attributes (PMA).

Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build.

Add driver for the Xilinx AXI Direct Memory Access (AXI DMA) controller

Add driver for Xilinx AXI Ethernet tri-mode (10/100/1000 Mb/s) MAC found

o Implement a bounce buffer based on device reserved memory.

Disable interrupts first and then set spinlock_count to 1.

Provide a template for busdma code for RISC-V.

Deactivate IRQ resource by calling to intr_deactivate_irq().

o Rewrite softdma_process_tx() of Altera SoftDMA engine driver

Add support for Cadence network controller found in HiFive Unleashed board.

Implement pic_pre_ithread(), pic_post_ithread().

In D19798#424970, @markj wrote:

The new diff doesn't modify the PLIC driver.

Interrupts have to be disabled in PLIC driver when we process it in the interrupt thread.

Sorry this is a different issue. I simply forgot to implement pre_ithread, post_ithread methods in the interrupt controller driver where we have to disable and enable interrupts. I will update patch shortly

First disable interrupts and then clear bits.

o Grab the number of devices supported by PLIC from FDT.

Grab timer frequency from FDT.

Avoid orphan sections between __bss_start and .(s)bss.

use sleep(9) instead of thread_suspend_one

coresight_allocate() and coresight_release() calls added

another attempt to handle failure case correctly

wrap lines that are longer than 79 characters

fix style issues (wrap long lines)

fix memory leak on failure

fix destroying device on failure
destroy mtx lock

correctly deregister osd thread on failure

deregister osd thread on failure

Use thread_suspend_one() instead of thread_suspend_switch()

Include sys/x86/include/specialreg.h

destroy the character device first, and then osd_thread_deregister()

Use bool literals
Move pmc_vm_initialize() just after pmc_md_initialize()

/dev/pmc* devices permissions changed to read-only

deregister thread OSD
use read-only permissions for /dev/pmc*

X1000 is a single-core IoT cpu released 3 years ago. X1000/E even newer. They are so nice, I bought 20 of them (only 5 USD each).
Since X1000 uses parts from jz4780, may be it is better to rename jz4780 to X1000 and remove SMP support.

o Add pmap lock around pmap_fault_fixup() to ensure other thread will not

Support RISC-V implementations that do not manage the A and D bits

Revert r339421 due to unintended files included to commit.

Support RISC-V implementations that do not manage the A and D bits

Remove unneeded parenthesis in pmap_fault_fixup()
Set PTE_X for a new entry in pmap_enter_quick_locked()

Invalidate TLB on a local hart.

Check if PTE is valid before setting A or D bits

Don't set PTE_A bit on a regular kernel mapping too

Don't set PTE_D bit even on kernel mappings of regular VM objects ahead of time
Don't call to vm_fault on PTE_A, PTE_D (2nd scheme) faults. Use pmap_fault_fixup() instead

Initialize interrupt priority to 0 on all sources.

Add support for the UART device found in lowRISC system-on-a-chip.

Fix issues pointed by markj

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