The pcie_discovery_data is device specific, move it to the softc.
Move the root memory to the softc and switch it to use bus_space.
While here create a common function to get the correct bus_space
details for a given bus/slot/func/reg combination.

Move the driver to dev/pci/controller/

what about dev/pci/controller/? linux does that.
We have a similar subdirectory for MMC drivers: dev/mmc/host/ that works well and keeps dev/mmc/ clean

move the driver by request from jhb@

In D23349#516026, @jhb wrote:

As with the xilinx driver, can we please not put MD and chipset-specific code in sys/dev/pci?

o Address mmel's comment.
o Don't override MSI methods since Andrew has fixed a bug in the ITS driver

Include pcI_n1sdp to the build

Add comment for MSI/MSIx

Override MSI/MSIx pcib methods so MSI allocation fail and INTx are used.
MSI/MSIx don't work for now

Address Andrew's comments: use kva_alloc/pmap_enter for non-device memory

Looks good

nice catch!

Rename the driver to dev/xilinx/xlnx_pcib.[ch] per request from jhb@

Looks good. Thank you!

Looks good.

Looks good

I also have a comment from jhb@:
@br typically we only route device interrupts to a single core since interrupt handlers generally assume they are not run concurrently (interrupt filters, ithreads will be single-threaded even if the interrupt is broadcast)
as Andy noted, you want to handle interrupt binding requests, but you also need to do something for the “default” case.
Not sure what INTRNG does, but on x86 we round-robin interrupts among CPUs when they are first setup.

In D21928#484096, @mhorne wrote:

In D21928#484089, @br wrote:

Why do we need to enable interrupts for all CPUs and not only current cpu?
where an interrupt will be signaled in that case?

PIC_ENABLE_INTR is called very seldomly, often only once while setting up the PIC during intr_setup_irq by the BSP. Since it is not called per-cpu, this function should handle enabling the interrupt for all active CPUs.
BBL sets all PLIC enable bits to 1 by default, whereas OpenSBI sets them to 0, which is how I noticed that APs weren't having their interrupts enabled.

looks good!

Why do we need to enable interrupts for all CPUs and not only current cpu?
where an interrupt will be signaled in that case?

Are these example of PLIC contexts?

interrupts-extended = <
				&cpu0_intc 0xffffffff
				&cpu1_intc 0xffffffff &cpu1_intc 9
				&cpu2_intc 0xffffffff &cpu2_intc 9
				&cpu3_intc 0xffffffff &cpu3_intc 9
				&cpu4_intc 0xffffffff &cpu4_intc 9>;

• Infer the tracing device based on compiler architecture (PT on amd64, Coresight on aarch64)
• Document all the pmctrace usage flags

I was looking at Linux driver before writing this one. Why don't they do the same ?

hart ID is recorded to pcpup->pc_hart. Could it be used ? i.e. PCPU_GET(hart) or pcpu_find(cpu)->pc_hart

Regenerate patch.

Regenerate patch.

Regenerate patch.

Regenerate patch.

Regenerate patch.

Regenerate patch.

Regenerate patch.

Regenerate patch.

Thanks!

I discussed with James Clarke jrtc27, it is fine

In D21439#469311, @andrew wrote:

Can you update the psci code to use the arm_smccc_* functions? We should only have one copy the functions to make smccc calls and you can consider psci to be based on it.