- User Since
- Nov 27 2014, 10:57 AM (286 w, 4 d)
Thu, May 21
Wed, May 20
Reuse DMAR busdma backend for SMMU with minimal changes. This backend completely eliminates bouncing. Changes to DMAR are:
o Rename dmar to iommu
o Rename ctx to iommu_device
o Some dmar-specific functions removed
Wed, May 6
we should also need to add these devices to riscv kernel config (at least random and console)
I tested in tinyemu. It works.
(tinyemu supports version 2 only)
Fri, May 1
Correct the size of asid bit set.
o Since we don't share TLB with the main CPU, implement our own ASID allocator.
o Add smmu_tlbi_asid() function that allows to invalidate entire SMMU TLB for a specific ASID.
Thu, Apr 30
I think keeping all IOMMU engines and the framework in a single place is a good idea. It is easy to find all the implementations. Similar to dev/mmc/host, dev/usb/controller etc. But I'm happy with arm64/iommu too.
Add a hardware overview to the header of smmu.c
Wed, Apr 29
Set ASID to a Context Descriptor. The ASID is generated by pmap.c and stored to pmap->pm_cookie.
This is a quick fix for the issue I had with TLB.
We need to check if SMMU asid space is equal to pmap asid space (they both either 8 or 16 bits wide).
Apr 19 2020
What is the reason for a fatal page fault when some CPUs are not fired?
Normally it should start with a single CPU in that case.
Mar 30 2020
Mar 13 2020
Compare to NULL
Mar 12 2020
Add a call to panic()
Mar 10 2020
Mar 7 2020
Hi Nicholas. I'm doing efforts to figure out why this is needed.
Why cpu_check_mmu() does not work for you and what are specific devmap use cases you have at Axiado?
Feb 11 2020
Feb 10 2020
The pcie_discovery_data is device specific, move it to the softc.
Move the root memory to the softc and switch it to use bus_space.
While here create a common function to get the correct bus_space
details for a given bus/slot/func/reg combination.
Move the driver to dev/pci/controller/
what about dev/pci/controller/? linux does that.
We have a similar subdirectory for MMC drivers: dev/mmc/host/ that works well and keeps dev/mmc/ clean
Feb 8 2020
Feb 7 2020
move the driver by request from jhb@
Feb 6 2020
Feb 5 2020
Feb 3 2020
Feb 1 2020
Jan 30 2020
o Address mmel's comment.
o Don't override MSI methods since Andrew has fixed a bug in the ITS driver
Include pcI_n1sdp to the build
Jan 29 2020
Add comment for MSI/MSIx
Override MSI/MSIx pcib methods so MSI allocation fail and INTx are used.
MSI/MSIx don't work for now
Jan 28 2020
Address Andrew's comments: use kva_alloc/pmap_enter for non-device memory
Jan 27 2020
Jan 24 2020
Jan 23 2020
Rename the driver to dev/xilinx/xlnx_pcib.[ch] per request from jhb@
Jan 17 2020
Dec 30 2019
Dec 29 2019
Looks good. Thank you!
Dec 4 2019
Nov 14 2019
Nov 11 2019
Nov 4 2019
Oct 28 2019
I also have a comment from jhb@:
@br typically we only route device interrupts to a single core since interrupt handlers generally assume they are not run concurrently (interrupt filters, ithreads will be single-threaded even if the interrupt is broadcast)
as Andy noted, you want to handle interrupt binding requests, but you also need to do something for the “default” case.
Not sure what INTRNG does, but on x86 we round-robin interrupts among CPUs when they are first setup.
Oct 25 2019
Why do we need to enable interrupts for all CPUs and not only current cpu?
where an interrupt will be signaled in that case?
Oct 15 2019
Oct 14 2019
Oct 11 2019
Oct 10 2019
Oct 8 2019
Are these example of PLIC contexts?
interrupts-extended = < &cpu0_intc 0xffffffff &cpu1_intc 0xffffffff &cpu1_intc 9 &cpu2_intc 0xffffffff &cpu2_intc 9 &cpu3_intc 0xffffffff &cpu3_intc 9 &cpu4_intc 0xffffffff &cpu4_intc 9>;