Address @markj comments. Thanks, Mark!

Address @jrtc27 comments

Add spinlock around DOMAINCFG acccess.

Add clock-frequency property to UART instead of defining fixed-clock

style: end of function return SUCCESS unless switch statement hit FAILURE

Resubmit updated patch

• Remove $FreeBSD$ tags
• Remove unused include headers
• Check if HWT hooks are installed before constructing data structures

Address @jrtc27 and @markj comments (Thanks!)

Address @markj comments

Switch coresight to EL2 otherwise it does not trace CPU mode.

In D40466#1056428, @andrew wrote:

How do you handle different conflicting modes? e.g. a user is tracing a pid & another tries to enable thread tracing. The hardware may not be able to perform both operations.

Prevent tracing the same proc by multiple users.

In D40477#957268, @andrew wrote:

This doesn't build when I add hwt and coresight to my kernel config

Due to pipeline design Coresight components could not be used for more than 1 concurrent tracing sessions.
Atomic counter of sessions added and limited to 1.

Use delayed children attach.
It seems the PHY needs extra 500ms to initialize before we probe for devices. Otherwise PCIB could not find a device (Intel NVME in my case).
So instead of waiting for 500ms, postpone the bus enumeration.

In D48133#1097519, @jrtc27 wrote:

Wait so you put up a patch to disable Sstc before an alternative was provided?

make reset driver optional
remove dtbs build

remove extra retval check

use snprintf() to ensure we don't overwrite buffer available

Per @mhorne suggestion, add device_get_unit() check;
Get virtual address of memory resource using rman_get_virtual().

add const qualifier to char *isa

Per @markj suggestion, construct the ISA string in the bhyve_init_platform() and then pass ready-to-use string to FDT code

In D48058#1095266, @jrtc27 wrote:

Do we really want one vm_cap_type entry per extension?

Add missing context!

I managed to convert the driver to newbus but noticed slower performance of NVME when flushing cache using bus_write_8().

• direct access to pointer: 97.5MB/s
• using bus_write_8(): 93.3MB/s

So I provided another mapping for a faster access. WDYT?
another idea is to extract the mapping from sc->res and access it directly?

In D47831#1091595, @br wrote:

In D47831#1091588, @mhorne wrote:

I strongly think this should be a newbus device driver. Unless there is some urgent need that it should be set up at SI_SUB_CPU?

This driver needed before threadinit() otherwise tid_alloc() won't work. It is needed even all cache ways in ccache driver are disabled (however the way 0 is always enabled). May be it flushes other L1/L2/L3 caches I am not sure, but from I saw the freebsd could not use memory that was just allocated in tid_alloc() without a flush. So this should go anywhere before SI_SUB_INTRINSIC.

In D47831#1091588, @mhorne wrote:

I strongly think this should be a newbus device driver. Unless there is some urgent need that it should be set up at SI_SUB_CPU?

This driver needed before threadinit() otherwise tid_alloc() won't work. It is needed even all cache ways in ccache driver are disabled (however the way 0 is always enabled). May be it flushes other L1/L2/L3 caches I am not sure, but from I saw the freebsd could not use memory that was just allocated in tid_alloc() without a flush. So this should go anywhere before SI_SUB_INTRINSIC.

Right, sorry:)

store both reg and bit in the hwreset *id