riscv: add custom T-HEAD dcache ops

[mhorne]

Summary

This is the first major errata we need to support in order to run on
current T-HEAD/XuanTie CPUs, e.g. the C906 or C910, found in several
existing RISC-V SBCs. With these custom dcache routines installed,
busdma can reliably communicate with devices which are not coherent
w.r.t. the CPU's data caches.

This patch introduces the first errata handling functions to identcpu.c,
and thus is forced to make some decisions about how this code is
structured. It will be amended with the changes that follow in the
series, yet I feel the final result is (unavoidably) somewhat clumsy. I
expect the CPU identification code will continue to evolve as more CPUs
and their errata are eventually supported.

T-HEAD specific code is added to a new file, and the custom instructions
can fortunately be enabled on a per-function basis.

[jrtc27]

sys/riscv/thead/thead.c

41

This won't build with older Clang, this was added quite recently

[mhorne]

Don't rely on new compiler features for the THEAD custom instructions. Instead, specify the raw bytes.

[jhb]

sys/riscv/riscv/identcpu.c

495

I would be tempted to use "handle" instead of "update" for the functions in this file, e.g. handle_cpu_errata_thead seems more accurate to me. These also might be more like quirks than errata per se. An errata is when the processor fails to implement its architecture. In this case T-HEAD is just implementing a variant architecture, so maybe handle_cpu_quirks() -> handle_thead_quirks() -> thead_setup_cache(). I might be tempted to just inline the body of the first new function into the second btw unless it is going to grow more things in the near future.

[jrtc27]

sys/riscv/thead/thead.c

61

If you use register __asm("t0") for va (or a temporary), like is done for SBI calls, you can let the register allocator do the move for you or, more likely, use t0 in the first place (and also not require marking it as clobbered).

[mhorne]

Better use of t0 register.

Use jhb's suggested naming.