vmd(4): Major driver refactoring

[mav]

Summary

• Re-implement pcib interface to use standard pci bus driver on top of vmd(4) instead of custom one.
• Re-implement memory/bus resource allocation to properly handle even complicated configurations.
• Re-implement interrupt handling to evenly distribute children's MSI/MSI-X interrupts between available vmd(4) MSI-X vectors and setup them to be handled by standard OS mechanisms with minimal overhead, except sharing when unavoidable.

Test Plan

Successfully tested on laptop with Intel Gen11 CPU (VMD device ID 0x9a0b) and single NVMe SSD, dual-booting with Windows 10.
Successfully tested on Supermicro X11DPI-NT motherboard with Xeon(R) Gold 6242R CPUs (VMD device ID 0x201d), simultaneously handling single NVMe SSD on one PCIe port and PLX bridge with 3 NVMe and 1 AHCI SSDs on another, including SSDs hot-plug and different interrupt settings.

[mav]

Limit the end of bus numbers range considering available BAR0 size.

[mav]

Provide VMD dma tag to all children devices, since host should see it as originator for all requests. It fixes operation with IOMMU enabled at least for directly connected devices. Devices behind a bridge still don't work right for me for some reason, despite receiving the same tag and IOMMU not reporting violations.