arm64: Support TBI in userspace
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Authored by andrew on Jul 30 2025, 4:57 PM.

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Reviewers

kib
harry.moulton_arm.com
manu
alc

Group Reviewers

arm64

Commits

rG4c6c27d3fb4a: arm64: Support TBI in userspace

Summary

To allow for Hardware-assisted AddressSanitizer (HWASAN) and future
work to enable MTE we need to enable TBI in userspace. As address space
that previously would have faulted will now not it could be considered
an ABI change so only enable for processes with a late enough revision.

Diff Detail

Repository

rG FreeBSD src repository

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Unit

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Build Status

Buildable 65850
Build 62733: arc lint + arc unit

Event Timeline

andrew created this revision.Jul 30 2025, 4:57 PM

Herald added a reviewer: manu. · View Herald TranscriptJul 30 2025, 4:57 PM

Herald added subscribers: emaste, imp. · View Herald Transcript

andrew requested review of this revision.Jul 30 2025, 4:57 PM

Harbormaster completed remote builds in B65850: Diff 159450.Jul 30 2025, 4:57 PM

andrew added a parent revision: D49119: arm64: tidy up Top-Byte-Ignore (TBI) in the kernel.Jul 30 2025, 4:57 PM

andrew added inline comments.

sys/arm64/arm64/efirt_machdep.c
254

imp added inline comments.Jul 30 2025, 5:19 PM

sys/arm64/arm64/efirt_machdep.c
278	We now change it to set TBI. Should the comment be reworked?
sys/arm64/arm64/pmap.c
9163	Why didn't you invalidate the tlb like you did elsewhere? Other places you don't say why

andrew added a reviewer: alc.Jul 30 2025, 5:26 PM

andrew added inline comments.

sys/arm64/arm64/efirt_machdep.c
278	I think the only change needed here is to also mention `curthread` with `curpmap`
sys/arm64/arm64/pmap.c
9163	I only invalidate the TLB on exec as the tcr value may have changed from & the TLB may have cached the value from before the exec. I don't clear it here as it's just setting the value the TLB would have previously used.