rtwn: add a register value for R92C_FPGA0_POWER_SAVE, and other bits
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Authored by adrian on Dec 6 2024, 11:56 PM.

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imp
bz

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rG35e63136a8c2: rtwn: add a register value for R92C_FPGA0_POWER_SAVE, and other bits

Summary

add a register value for the R92C_FPGA0_POWER_SAVE register
add the field names and mask
add a mask for the 40MHz upper/lower bits in R92C_RMRR; I think I need to debug and overhaul the 20/40MHz config path to get 40MHz working right.

Local testing:

rtl8188eu, sta mode
rtl8192cu, sta mode

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Repository

rG FreeBSD src repository

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Build Status

Buildable 61016
Build 57900: arc lint + arc unit

Event Timeline

adrian created this revision.Dec 6 2024, 11:56 PM

Herald added a subscriber: imp. · View Herald TranscriptDec 6 2024, 11:56 PM

adrian requested review of this revision.Dec 6 2024, 11:56 PM

Harbormaster completed remote builds in B61016: Diff 147658.Dec 6 2024, 11:56 PM

adrian added a parent revision: D47938: rtwn: remove unused rate configuration code for management traffic..Dec 6 2024, 11:58 PM

adrian added a child revision: D47978: rtwn: add tx power training for RTL8812/RTL8821.Dec 7 2024, 3:50 PM

imp accepted this revision.Dec 12 2024, 6:27 PM

This revision is now accepted and ready to land.Dec 12 2024, 6:27 PM

"I think ..." doesn't sound like it needs to be a commit message but a personal note. Maybe update it before committing.

adrian closed this revision.Dec 18 2024, 7:32 PM

adrian added a commit: rG35e63136a8c2: rtwn: add a register value for R92C_FPGA0_POWER_SAVE, and other bits.

Revision Contents
Changeset List

Path

Size

sys/

dev/

rtwn/

rtl8192c/

r92c_chan.c

3 lines

r92c_reg.h

7 lines

Diff 147658

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sys/dev/rtwn/rtl8192c/r92c_chan.c