arm64: Add a multiple TLBI workaround

[andrew]

Summary

The Arm Cortex-A55, Cortex-A76, and Cortex-A510 CPUs have errata that
require multiple TLBI, DSB instructions to workaround.

Add support to pmap to implement these. As it appears that all
affected TLBI calls are via pmap.c this should be sufficient.

Sponsored by: Arm Ltd

[alc]

In principle, I am okay with this change. However, I do have some questions.

I am under the impression that Linux no longer applies a similar workaround by default. That is, you have to explicitly configure it before compiling. Specifically, ARM ultimately categorized these errata as "rare", and Linux does not enable workarounds for rare errata by default. Am I out of date on the handling of these errata under Linux? Should we have a means to explicitly disable or enable such workarounds? Is the Neoverse N1 core affected too?

The low-level details of the errata differ between the A55 and A76, but the common thread is that the kernel is changing the mapped physical address. Really, the only common case of that is a write-fault on a copy-on-write mapping. In that case, the hardware bug should be innocuous. The A55 bug involves a write access by another core not completing as early as it should, but write accesses are disallowed by virtue of the page being copy-on-write. The A76 bug involves loads being misordered, which again shouldn't matter if the page was read-only.

sys/arm64/arm64/pmap.c

1753

Isn't this specifying the wrong part?

[andrew]

• Fix a midr check
• Rebase past D52358 so the workaround is disabled by default, but can be enabled

[andrew]

I've added support to manage which features/errata are enabled at boot time & used this to disable this workaround by default, but let the user enable it if they are affected by it.