Differential D52186

arm64: Cleanup enabling the MMU
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Authored by andrew on Aug 27 2025, 5:02 PM.

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Reviewers

manu
kib
alc
markj

Group Reviewers

Summary

Add a missing data barrier before invalidating the tlb and relax the
barrier afterwards. This ensures all stores to the page tables have
completed, and no loads or stores afterwards are moved before the tlbi.

While here move an instruction barrier after all msr instructions in
start_mmu. These may not complete until the isb so it's safer to have
it complete before invalidating the TLB.

Sponsored by: Arm Ltd

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Repository

rG FreeBSD src repository

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Build Status

Buildable 66569
Build 63452: arc lint + arc unit

Event Timeline

andrew created this revision.Aug 27 2025, 5:02 PM

Herald added a reviewer: manu. · View Herald TranscriptAug 27 2025, 5:02 PM

Herald added subscribers: emaste, imp. · View Herald Transcript

andrew requested review of this revision.Aug 27 2025, 5:02 PM

Harbormaster completed remote builds in B66569: Diff 161050.Aug 27 2025, 5:02 PM

andrew added a parent revision: D52185: arm64: Remove cpu_tlb_flushID now it's unused.Aug 27 2025, 5:02 PM

andrew added a child revision: D52187: arm64: Add a function to check a range of CPU revs.

andrew added reviewers: kib, alc, markj.Aug 28 2025, 9:37 AM

alc added inline comments.Aug 28 2025, 5:07 PM

sys/arm64/arm64/locore.S
974	After this change, what purpose does this dsb serve? I suspect that the existence of this dsb is why there wasn't a later one.

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sys/

arm64/

arm64/

6 lines

Diff 161050

sys/arm64/arm64/locore.S

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