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arm64: Cleanup enabling the MMU
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Authored by andrew on Aug 27 2025, 5:02 PM.
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Details

Reviewers
manu
kib
alc
markj
Group Reviewers
arm64
Summary

Add a missing data barrier before invalidating the tlb and relax the
barrier afterwards. This ensures all stores to the page tables have
completed, and no loads or stores afterwards are moved before the tlbi.

While here move an instruction barrier after all msr instructions in
start_mmu. These may not complete until the isb so it's safer to have
it complete before invalidating the TLB.

Sponsored by: Arm Ltd

Diff Detail

Repository
rG FreeBSD src repository
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Unit
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Build Status
Buildable 66569
Build 63452: arc lint + arc unit

Event Timeline

sys/arm64/arm64/locore.S
974

After this change, what purpose does this dsb serve? I suspect that the existence of this dsb is why there wasn't a later one.