The calculation of table sizes for the GICv3 was wrong "Indiana Jones" style: The width of the bit field is reported one less than it's value.
This patch makes interrupt work on my T41s G6 SnapDragon, but I have no idea if/how it works on any other hardware.
The cache bits cannot be written on this platform, and it is not obvious to me if we should even be messing with them in the first place, or trust the default offered by the hardware.
I cannot tell if the ITS_FLAGS_ERRATA_CAVIUM_22375 workaround is still necessary, to me the comment sounds a little bit like it works around the wrong math ?
I renamed the "page_size" variable to "gic_page_size" for clarity.