arm: Add ARM PL022 Synchronous Serial Port driver
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Authored by jhibbits on May 15 2024, 6:41 PM.

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andrew
manu

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ARM

Summary

ARM pl022 is a general purpose synchronous serial port controller,
implementing SPI, SSI, and National Microwire frame formats. The driver
currently only supports SPI format.

One limitation of the driver is that hardware only raises an interrupt
if the RX queue contains at least 4 characters, so fewer than 4
characters in the queue may result in data never being received.

Obtained from: Juniper Networks, Inc.

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rG FreeBSD src repository

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Buildable 57719
Build 54607: arc lint + arc unit

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jhibbits created this revision.May 15 2024, 6:41 PM

Herald added a reviewer: andrew. · View Herald TranscriptMay 15 2024, 6:41 PM

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jhibbits requested review of this revision.May 15 2024, 6:41 PM

Harbormaster completed remote builds in B57719: Diff 138586.May 15 2024, 6:41 PM

br added a subscriber: br.Jun 3 2024, 10:31 AM

br added inline comments.

sys/arm/arm/pl022.h
46	For the bit definition I usually omit prefix (i.e. PL022_), and put extra space after tab. that allows easier navigation with bare eye. example sys/arm64/iommu/smmureg.h

One limitation of the driver is that hardware only raises an interrupt if the RX queue contains at least 4 characters, so fewer than 4 characters in the queue may result in data never being received.

Do you not receive the SSPRTINTR interrupt?

sys/arm/arm/pl022.c
135
216
229	ditto

In D45211#1036945, @andrew wrote:

One limitation of the driver is that hardware only raises an interrupt if the RX queue contains at least 4 characters, so fewer than 4 characters in the queue may result in data never being received.

Do you not receive the SSPRTINTR interrupt?

Nope, and it's documented in the reference (DDI0194H):

3.4.1
SSPRXINTR
The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.

sys/arm/arm/pl022.c
135	Oops, and I'm usually the one to give grief over style(9), myself. Will take a closer pass, along with the others.

In D45211#1036969, @jhibbits wrote:

3.4.1
SSPRXINTR
The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.

That's a different interrupt, see 3.4.4 SSPRTINTR of the same document.

In D45211#1036980, @andrew wrote:

In D45211#1036969, @jhibbits wrote:

3.4.1
SSPRXINTR
The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.

That's a different interrupt, see 3.4.4 SSPRTINTR of the same document.

Ah, sorry, I had misread. Apparently I don't get the SSPRTINTR on the device I have, as it seems to time out (2 second timeout) on 3-byte messages, and the interrupt is enabled. Maybe it's an issue with my particular device?

Address style feedback.

Harbormaster completed remote builds in B58132: Diff 139697.Jun 10 2024, 6:58 PM

Do you need interrupts in this driver? It looks like Linux only uses them when using DMA to transfer data to/from the device.

In D45211#1040937, @andrew wrote:

Do you need interrupts in this driver? It looks like Linux only uses them when using DMA to transfer data to/from the device.

Maybe not, but this is consistent with every other SPI driver in the tree.