Add the BCM2835-specific clock data (bcm2835_cprman_clocks.c) and the
chip driver (bcm2835_cprman_drv.c), and register all new source files
in the arm32 and arm64 build systems.
bcm2835_cprman_clocks.c defines:
- bcm2835_periph_clks[]: GP0/GP1/GP2, PWM, PCM peripheral clocks
- bcm2835_plls[]: PLLA, PLLC, PLLD with A2W register offsets, NaN filter coefficients, and XOSC enable bits
- bcm2835_pll_channels[]: all per-PLL output dividers (dsi0, ccp2, core, per for PLLA; core0/1/2, per for PLLC; dsi0/1, core, per for PLLD)
- bcm2835_stub_clks[]: 0 Hz placeholders for gnd, testdebug0/1, pllh_aux
All tables are exported as bcm2835_cprman_clk_data.
bcm2835_cprman_drv.c is reduced to probe/attach only; attach assigns
sc->clk_data = &bcm2835_cprman_clk_data and delegates to the shared
bcm_cprman_attach(). The parent clock name is corrected from
"hdmi_aux" to "pllh_aux" and the driver init order is changed from
BUS_PASS_ORDER_MIDDLE to BUS_PASS_ORDER_LATE so that all simplebus
children (including the OSC fixed-clock node) are attached first.
files.bcm283x and files.arm64 are updated to include all six new
source files under the CPRMAN clock controller section.
Signed-off-by: perdixky <3293789706@qq.com>