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Differential D42910

riscv: tweak SoC-specific conf organization
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Authored by mhorne on Dec 5 2023, 6:38 PM.
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jrtc27
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riscv
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rGbd79cafe70c8: riscv: tweak SoC-specific conf organization
Summary

Hide some lines from the main GENERIC files by mimicking arm64's model.

I do not have any intention of creating a std.riscv or SIFIVE
configuration file at this time.

Diff Detail

Repository
rG FreeBSD src repository
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Lint Passed
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Build Status
Buildable 54797
Build 51686: arc lint + arc unit

Event Timeline

mhorne created this revision.Dec 5 2023, 6:38 PM
Herald added a subscriber: imp. · View Herald TranscriptDec 5 2023, 6:38 PM
mhorne requested review of this revision.Dec 5 2023, 6:38 PM
Harbormaster completed remote builds in B54797: Diff 131038.Dec 5 2023, 6:38 PM
mhorne added a child revision: D42911: riscv: add more dump features to GENERIC.Dec 5 2023, 6:38 PM
jrtc27 accepted this revision.Dec 5 2023, 6:40 PM
jrtc27 added a subscriber: jrtc27.

std.sifive not being what you'd expect it to be bugged me in the past, thanks for the cleanup :)

This revision is now accepted and ready to land.Dec 5 2023, 6:40 PM
Closed by commit rGbd79cafe70c8: riscv: tweak SoC-specific conf organization (authored by mhorne). · Explain WhyDec 5 2023, 7:31 PM
This revision was automatically updated to reflect the committed changes.
mhorne added a commit: rGbd79cafe70c8: riscv: tweak SoC-specific conf organization.

Revision Contents
Changeset List

PathSize
sys/
riscv/
conf/
18 lines
7 lines
15 lines
sifive/

Diff 131038

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sys/riscv/conf/GENERIC

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sys/riscv/conf/std.allwinner

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sys/riscv/conf/std.sifive

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sys/riscv/sifive/std.sifive

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