riscv: tweak SoC-specific conf organization

[mhorne]

Summary

Hide some lines from the main GENERIC files by mimicking arm64's model.

I do not have any intention of creating a std.riscv or SIFIVE
configuration file at this time.

[jrtc27]

std.sifive not being what you'd expect it to be bugged me in the past, thanks for the cleanup :)