Resubmit updated patch

• Remove $FreeBSD$ tags
• Remove unused include headers
• Check if HWT hooks are installed before constructing data structures

Address @jrtc27 and @markj comments (Thanks!)

Address @markj comments

Switch coresight to EL2 otherwise it does not trace CPU mode.

In D40466#1056428, @andrew wrote:

How do you handle different conflicting modes? e.g. a user is tracing a pid & another tries to enable thread tracing. The hardware may not be able to perform both operations.

Prevent tracing the same proc by multiple users.

In D40477#957268, @andrew wrote:

This doesn't build when I add hwt and coresight to my kernel config

Due to pipeline design Coresight components could not be used for more than 1 concurrent tracing sessions.
Atomic counter of sessions added and limited to 1.

Use delayed children attach.
It seems the PHY needs extra 500ms to initialize before we probe for devices. Otherwise PCIB could not find a device (Intel NVME in my case).
So instead of waiting for 500ms, postpone the bus enumeration.

In D48133#1097519, @jrtc27 wrote:

Wait so you put up a patch to disable Sstc before an alternative was provided?

make reset driver optional
remove dtbs build

remove extra retval check

use snprintf() to ensure we don't overwrite buffer available

Per @mhorne suggestion, add device_get_unit() check;
Get virtual address of memory resource using rman_get_virtual().

add const qualifier to char *isa

Per @markj suggestion, construct the ISA string in the bhyve_init_platform() and then pass ready-to-use string to FDT code

In D48058#1095266, @jrtc27 wrote:

Do we really want one vm_cap_type entry per extension?

Add missing context!

I managed to convert the driver to newbus but noticed slower performance of NVME when flushing cache using bus_write_8().

• direct access to pointer: 97.5MB/s
• using bus_write_8(): 93.3MB/s

So I provided another mapping for a faster access. WDYT?
another idea is to extract the mapping from sc->res and access it directly?

In D47831#1091595, @br wrote:

In D47831#1091588, @mhorne wrote:

I strongly think this should be a newbus device driver. Unless there is some urgent need that it should be set up at SI_SUB_CPU?

This driver needed before threadinit() otherwise tid_alloc() won't work. It is needed even all cache ways in ccache driver are disabled (however the way 0 is always enabled). May be it flushes other L1/L2/L3 caches I am not sure, but from I saw the freebsd could not use memory that was just allocated in tid_alloc() without a flush. So this should go anywhere before SI_SUB_INTRINSIC.

In D47831#1091588, @mhorne wrote:

I strongly think this should be a newbus device driver. Unless there is some urgent need that it should be set up at SI_SUB_CPU?

This driver needed before threadinit() otherwise tid_alloc() won't work. It is needed even all cache ways in ccache driver are disabled (however the way 0 is always enabled). May be it flushes other L1/L2/L3 caches I am not sure, but from I saw the freebsd could not use memory that was just allocated in tid_alloc() without a flush. So this should go anywhere before SI_SUB_INTRINSIC.

Right, sorry:)

store both reg and bit in the hwreset *id

copyright and style(9)

extract paddr on each page assuming the range is not contiguous

In D47412#1088559, @dev_submerge.ch wrote:

Also I suspect the input signal levels to be backwards now, please report your findings. The recorded signal should be loudest for "-10dBV" and quietest with "LowGain".

On the Input front, I have inserted Shure SM7B into External card Input 1, and I barely hear myself in Audacity. Slighly more loud on LowGain compare to +4dBu, but still very low on both. I could not set -10dBV because of off-by-one error somewhere (I guess).

In D47412#1087403, @dev_submerge.ch wrote:

In D47412#1086254, @br wrote:

On the "-10dbV" problem I could suggest to rename this to "minus10dbv" (and "plus4dbu as well).

Now that I think of it, we also have negative integer values in sysctl. Given that, it should be acceptable to use "-10dBV". It is quite a bit more readable and closer to RME / standard signal level terminology.

Could you please try to set "-10dBV" in a su -l session, to check whether this is a sudo problem? I read through the code again and didn't find any possible cause.

In D47688#1087747, @markj wrote:

In D47688#1087739, @jrtc27 wrote:

Perhaps worth mentioning in the commit message that RISC-V is unusual in allowing the TLB to cache invalid PTEs

I'm not sure that that's exactly what's happening - it might be that the core is caching translation structures (and this is certainly not specific to riscv) and requires a sfence.vma for PTE updates to be visible.

In fact, we might still want to issue a local sfence.vma when overwriting an invalid PTE in pmap_enter(), to avoid the overhead of spurious faults on first access. It's hard to say without some data on how common such faults are.

Works to me on SiFive Premier P550 (no hacky TLB flush needed anymore). Thanks!

On the "-10dbV" problem I could suggest to rename this to "minus10dbv" (and "plus4dbu as well).

(Note that default setting (-10dBV) is loudest, then +4dbU is lower, and HighGain is lowest volume)

Interesting, should be the other way round. The linux code doesn't seem to label these explicitly, which is why I expected the 0 value to be safe (quiet) similar to HDSP 9632. Chances are the input and output levels work the same and are in wrong order too, could you check them?

On travel currently -- will look next week.

Great work, thanks!

Regenerate

fix shift value of a register and remove bogus ones

unlock spin mutex when no interrupts found during APLIC CLAIM request

great idea, and happy to test (and actually use) if you can adopt to hdspe!

Regenerate

Instead of using static address for device tree blob, locate it just after bootrom image dynamically.

Address comments

Remove unrelated arm64/amd64 changes

Address markj@ comments, Thanks Mark