riscv timer: fix interrupt handing

[br]

Summary

We have got a hardware (Codasip A730) that does not clear the timer pending bit by CSR request from supervisor, instead it expects us to do an SBI call.

Based on the spec the behavior of the hardware is correct as STIP is read-only in SIP:
https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc?plain=1#L401

Upon reception of SBI request, the machine mode software clears the STIP in MIP:
https://github.com/riscv/riscv-isa-manual/blob/main/src/machine.adoc?plain=1#L1464

Test Plan

Tested on Codasip