riscv timer: fix interrupt handling.

Based on the spec the STIP bit of SIP register is read-only.

To clear STIP bit from supervisor we have to do an SBI call to firmware.
Upon reception of SBI request, the machine-mode firmware clears the STIP
bit in the MIP register.

This fixes operation on Codasip A730.

Reviewed by: mhorne
Differential Revision: https://reviews.freebsd.org/D49487

(cherry picked from commit 6d58c670060a17817fa0c8ebf4e7543c3d2b4523)