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Differential D4371

Correct ifdefs in arm/mv/timer.c
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Authored by bsz_semihalf.com on Dec 4 2015, 1:06 PM.
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andrew
imp
• ian
Summary

SOC_MV_ARMADAXP ifdefs in timer code needed enhancement with
SOC_MV_ARMADA38X so as to avoid using wrong definitions, unrelated
to Armada38x.

Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>

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rS FreeBSD src repository - subversion
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bsz_semihalf.com updated this revision to Diff 10732.Dec 4 2015, 1:06 PM
bsz_semihalf.com retitled this revision from to Correct ifdefs in arm/mv/timer.c.
bsz_semihalf.com updated this object.
bsz_semihalf.com edited the test plan for this revision. (Show Details)
bsz_semihalf.com added reviewers: • ian, imp.
bsz_semihalf.com set the repository for this revision to rS FreeBSD src repository - subversion.
bsz_semihalf.com added a project: ARM.
bsz_semihalf.com added a subscriber: zbb.
Herald added a subscriber: andrew. · View Herald TranscriptDec 4 2015, 1:06 PM
bsz_semihalf.com added a parent revision: D4370: Add interrupt line for EHCI USB errors in Armada38x.Dec 4 2015, 1:06 PM
bsz_semihalf.com added a child revision: D4372: Mark gpio optional in files.mv; edit Marvell's kernconfs.
bsz_semihalf.com updated this revision to Diff 10852.Dec 7 2015, 8:37 AM
bsz_semihalf.com updated this object.
andrew accepted this revision.Dec 10 2015, 9:27 AM
andrew added a reviewer: andrew.
This revision is now accepted and ready to land.Dec 10 2015, 9:27 AM
bsz_semihalf.com edited parent revisions, added: D4369: Enhance attachment of ehci_mv driver; removed: D4370: Add interrupt line for EHCI USB errors in Armada38x.Dec 11 2015, 12:49 PM
bsz_semihalf.com added a child revision: D4375: Enable USB in kernconf of Armada38x.
bsz_semihalf.com removed a child revision: D4372: Mark gpio optional in files.mv; edit Marvell's kernconfs.Dec 15 2015, 10:24 AM
bsz_semihalf.com closed this revision.Jan 26 2016, 3:59 PM

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sys/
arm/
mv/
18 lines

Diff 10852

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sys/arm/mv/timer.c

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
#include <arm/mv/mvvar.h> #include <arm/mv/mvvar.h>
#include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h> #include <dev/ofw/ofw_bus_subr.h>
#define INITIAL_TIMECOUNTER (0xffffffff) #define INITIAL_TIMECOUNTER (0xffffffff)
#define MAX_WATCHDOG_TICKS (0xffffffff) #define MAX_WATCHDOG_TICKS (0xffffffff)
#if defined(SOC_MV_ARMADAXP) #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */ #define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
#else #else
#define MV_CLOCK_SRC get_tclk() #define MV_CLOCK_SRC get_tclk()
#endif #endif
struct mv_timer_softc { struct mv_timer_softc {
struct resource * timer_res[2]; struct resource * timer_res[2];
bus_space_tag_t timer_bst; bus_space_tag_t timer_bst;
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
} }
static int static int
mv_timer_attach(device_t dev) mv_timer_attach(device_t dev)
{ {
int error; int error;
void *ihl; void *ihl;
struct mv_timer_softc *sc; struct mv_timer_softc *sc;
#if !defined(SOC_MV_ARMADAXP) #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_cause, irq_mask; uint32_t irq_cause, irq_mask;
#endif #endif
if (timer_softc != NULL) if (timer_softc != NULL)
return (ENXIO); return (ENXIO);
sc = (struct mv_timer_softc *)device_get_softc(dev); sc = (struct mv_timer_softc *)device_get_softc(dev);
timer_softc = sc; timer_softc = sc;
Show All 14 Lines#endif
if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
mv_hardclock, NULL, sc, &ihl) != 0) { mv_hardclock, NULL, sc, &ihl) != 0) {
bus_release_resources(dev, mv_timer_spec, sc->timer_res); bus_release_resources(dev, mv_timer_spec, sc->timer_res);
device_printf(dev, "Could not setup interrupt.\n"); device_printf(dev, "Could not setup interrupt.\n");
return (ENXIO); return (ENXIO);
} }
mv_setup_timers(); mv_setup_timers();
#if !defined(SOC_MV_ARMADAXP) #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
irq_cause &= IRQ_TIMER0_CLR; irq_cause &= IRQ_TIMER0_CLR;
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
irq_mask |= IRQ_TIMER0_MASK; irq_mask |= IRQ_TIMER0_MASK;
irq_mask &= ~IRQ_TIMER1_MASK; irq_mask &= ~IRQ_TIMER1_MASK;
write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Linesmv_set_timer_rel(uint32_t timer, uint32_t val)
bus_space_write_4(timer_softc->timer_bst, bus_space_write_4(timer_softc->timer_bst,
timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
} }
static void static void
mv_watchdog_enable(void) mv_watchdog_enable(void)
{ {
uint32_t val, irq_cause; uint32_t val, irq_cause;
#if !defined(SOC_MV_ARMADAXP) #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_mask; uint32_t irq_mask;
#endif #endif
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
irq_cause &= IRQ_TIMER_WD_CLR; irq_cause &= IRQ_TIMER_WD_CLR;
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
#if defined(SOC_MV_ARMADAXP) #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
#else #else
irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
irq_mask |= IRQ_TIMER_WD_MASK; irq_mask |= IRQ_TIMER_WD_MASK;
write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
val = read_cpu_ctrl(RSTOUTn_MASK); val = read_cpu_ctrl(RSTOUTn_MASK);
val |= WD_RST_OUT_EN; val |= WD_RST_OUT_EN;
write_cpu_ctrl(RSTOUTn_MASK, val); write_cpu_ctrl(RSTOUTn_MASK, val);
#endif #endif
val = mv_get_timer_control(); val = mv_get_timer_control();
val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO; val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
#if defined(SOC_MV_ARMADAXP) #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val |= CPU_TIMER_WD_25MHZ_EN; val |= CPU_TIMER_WD_25MHZ_EN;
#endif #endif
mv_set_timer_control(val); mv_set_timer_control(val);
} }
static void static void
mv_watchdog_disable(void) mv_watchdog_disable(void)
{ {
uint32_t val, irq_cause; uint32_t val, irq_cause;
#if !defined(SOC_MV_ARMADAXP) #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_mask; uint32_t irq_mask;
#endif #endif
val = mv_get_timer_control(); val = mv_get_timer_control();
val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
mv_set_timer_control(val); mv_set_timer_control(val);
#if defined(SOC_MV_ARMADAXP) #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
#else #else
val = read_cpu_ctrl(RSTOUTn_MASK); val = read_cpu_ctrl(RSTOUTn_MASK);
val &= ~WD_RST_OUT_EN; val &= ~WD_RST_OUT_EN;
write_cpu_ctrl(RSTOUTn_MASK, val); write_cpu_ctrl(RSTOUTn_MASK, val);
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
{ {
uint32_t val; uint32_t val;
mv_set_timer_rel(1, INITIAL_TIMECOUNTER); mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
mv_set_timer(1, INITIAL_TIMECOUNTER); mv_set_timer(1, INITIAL_TIMECOUNTER);
val = mv_get_timer_control(); val = mv_get_timer_control();
val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
#if defined(SOC_MV_ARMADAXP) #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
/* Enable 25MHz mode */ /* Enable 25MHz mode */
val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN; val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
#endif #endif
mv_set_timer_control(val); mv_set_timer_control(val);
timers_initialized = 1; timers_initialized = 1;
} }