Enable SCU unit for Armada38x

[bsz_semihalf.com]

Summary

Valid SCU operation is necessary for SMP interoperability. Initialization
function armada38x_enable_scu() was added to arm/mv/armada38x/armada38x.c
file.

Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <[e-mail]>

[andrew]

sys/arm/mv/armada38x/armada38x.c

113 ↗

(On Diff #10349)

if (rv != 0)

117 ↗

(On Diff #10349)

Why 0x30?

[imp]

sys/arm/mv/armada38x/armada38x.c

116 ↗

(On Diff #10349)

The Linux kernel has an option to enable this which states:

This option enables the workaround for erratum 764369 affecting Cortex-A9 MPCore with two or more processors (all current revisions). Under certain timing circumstances, a data cache line maintenance operation by MVA targeting an Inner Shareable memory region may fail to proceed up to either the Point of Coherency or to the Point of Unification of the system. This workaround adds a DSB instruction before the relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU.

Is there another ptach with the dsb instruction? Or do we always do it so that's not needed.

Also, is there a link to this information from arm? I could only find http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf which had very good information about it, but not a link back to arm when I just googled it. Looking at the startup code for the imx6, it's using symbolic names where you use magic numbers below. Maybe this would be a good candidate to be a function in locore for all A9 cores?

[bsz_semihalf.com]

sys/arm/mv/armada38x/armada38x.c

116 ↗

(On Diff #10349)

You're right, better place for it would be somewhere in code common for other platforms that use A9. I did neither find original ARM documentation for this, but here is some deeper explanation.
In fact I reimplemented it as a part of SCU enabling procedure without delving deeper into the issue it fixes, so better if I get rid of that from this commit. Then better patch (perhaps to locore) with proper dsb barriers (we don't have them, afaik) could be prepared.

[andrew]

sys/arm/mv/armada38x/armada38x.c

117 ↗

(On Diff #10440)

Erratum 764369 is in the ARM Cortex-A9 processors Software Developers Errata Notice. It seems to be present in all Cortex-A9 revisions so it shouldn't matter which revision you look at.

[• ian]

there are a variety of cortex-a9 common routines we should be able to factor out into common code at this point for things like SCU startup, but I don't think that needs to be part of this work.

sys/arm/mv/armada38x/armada38x.c

117 ↗

(On Diff #10440)

Yes, we do have the dsb() part of that erratum fix in place already, all the cache functions in cpu-v6.h begin and end with dsb().