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gicv3_its: Flush cache after allocating ITT memory
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Authored by mindal_semihalf.com on Apr 29 2021, 10:19 AM.

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Summary

It has to be zeroed before committing it to device.
We do that by allocating it with M_ZERO, but there was no memory barrier or cache flush to ensure its sees it zeroed.
This fixes MSIX on LS1028A SoC.

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R10 FreeBSD src repository
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Does this need to be done in all cases, or just when the ITS is not cache-coherent?

Does this need to be done in all cases, or just when the ITS is not cache-coherent?

Good question. I checked and Linux does this flush unconditionally.
With that being said our driver worked on cache-coherent devices without it.
Updated the revision to do the flush on non cache-coherent devices only

sys/arm64/arm64/gicv3_its.c
1202

I think we want a dsb(ishst); in the else case to ensure any previous writes to itt are complete. We might get it via the spinlock below, but shouldn't rely on it.

sys/arm64/arm64/gicv3_its.c
1202

I though about it and I don't think it is necessary here.
Before itt is committed to the ITS its_cmd_sync will be called, which does dsb(ishst); for cache-coherent devices.

This revision is now accepted and ready to land.Apr 30 2021, 1:50 PM