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Differential D48317

ARM64 GICv3 Cache bits
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Authored by phk on Sat, Jan 4, 1:45 PM.

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Reviewers
andrew
jrtc27
manu
Summary

This is the minimal subset of D478819 relating only to the cache bits.

Attempt to set the cache bits to GITS_BASER_CACHE_RAWAWB, but respect that sub-field may be read-only.

This works on my T14s Snapdragon machine.

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rG FreeBSD src repository
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Event Timeline

phk created this revision.Sat, Jan 4, 1:45 PM
Herald added a reviewer: manu. · View Herald TranscriptSat, Jan 4, 1:45 PM
Herald added subscribers: emaste, imp. · View Herald Transcript
phk requested review of this revision.Sat, Jan 4, 1:45 PM
andrew added inline comments.Sat, Jan 4, 1:59 PM
sys/arm64/arm64/gicv3_its.c
672

I don't understand this

phk added inline comments.Sat, Jan 4, 2:50 PM
sys/arm64/arm64/gicv3_its.c
672

As I explained in D478819: ARM's spec does not mandate/guarantee that the cache bits can be modified.

Therefore the value we write, be it zero in case of ITS_FLAGS_ERRATA_CAVIUM_22375 or RAWAWB otherwise, may not be what we read back.

QED: We should not ENXIO if the cache bits we read differ from the cache bits we wrote.

jrtc27 added inline comments.Sat, Jan 4, 5:15 PM
sys/arm64/arm64/gicv3_its.c
672

No, Andy’s point is the parentheses are in the wrong place so this is nonsensical.

phk updated this revision to Diff 148778.Sat, Jan 4, 7:44 PM

Changed != to ^ in write-read-back check.

sys/arm64/arm64/gicv3_its.c
672

Ohh, duH! I forgot to change the != to ^.

new patch in a sec.

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arm64/
arm64/
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Diff 148778

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sys/arm64/arm64/gicv3_its.c

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