INFRACFG provides the clock muxes and gates of the infrastructure
peripherals, and is their reset controller (the binding requires
#reset-cells). It attaches after TOPCKGEN.
The resets come in three banks, each with an assert register, a deassert
register at +4 and a status register at +8. Reset id n is bit n % 32 of
bank n / 32. Bank 0 at 0x70 is the one MediaTek's TF-A uses for the
TRNG [1]. Banks 1 (0x80) and 2 (0x90) were found on a Banana Pi BPI-R3
by resetting known blocks.
The clocks follow the MT7986 drivers of Linux [2] and U-Boot [3], which
were used for hardware facts only, with two changes:
- SPI1's clock selection uses spim_mst_sel instead of spi_sel, as in MediaTek's SDK [4], the "sel-clk" of spi1 in the DTS, and Linux's MT7981 driver [5].
- The security engine clocks never stop. OP-TEE uses them, and MediaTek marks them critical [6].
The node is also a syscon. That interface is not provided yet.
[1] https://github.com/mtk-openwrt/arm-trusted-firmware/blob/a229810586d8/plat/mediatek/mt7986/include/mt7986_def.h
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt7986-infracfg.c?h=v7.1
[3] https://source.denx.de/u-boot/u-boot/-/blob/v2025.10/drivers/clk/mediatek/clk-mt7986.c
[4] https://github.com/mediatek/mtk-openwrt-feeds/blob/f185b9c74f1d/21.02/files/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7986.c
[5] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt7981-infracfg.c?h=v7.1
[6] https://github.com/mediatek/mtk-openwrt-feeds/blob/f185b9c74f1d/25.12/files/target/linux/mediatek/patches-6.12/999-clk-05-clk-mediatek-mt7986-mark-sej-clks-as-critical.patch
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