TOPCKGEN provides the fixed dividers of the PLL outputs and the top
level muxes. Each mux field has a gate bit, is written through
set/clear registers and is latched through an update register. The
bus, DRAM and 26 MHz system clocks never stop. TOPCKGEN attaches after
APMIXEDSYS.
The layout follows the MT7986 clock drivers of Linux [1] and U-Boot [2],
which were used for hardware facts only. Both divide top_net2pll_d3_d2
by 2, while its name and MediaTek's SDK [3] suggest 6. This is not
verified on hardware.
The node is also a syscon. That interface is not provided yet, since no
MT7986 node uses it.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt7986-topckgen.c?h=v7.1
[2] https://source.denx.de/u-boot/u-boot/-/blob/v2025.10/drivers/clk/mediatek/clk-mt7986.c
[3] https://github.com/mediatek/mtk-openwrt-feeds/blob/f185b9c74f1d/21.02/files/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7986.c
Sponsored by: Alchemilla Ventures Private Limited