Add the eight MT7986 PLLs, all fed by the 40 MHz crystal. The CPU PLL
never stops. APMIXEDSYS attaches after the fixed clocks so that the CPU
PLL's reference reaches the crystal.
The rates are the ones set by TF-A BL2. The register layout, the
enable sequence and the reset bar bit (CON0 bit 24 on NET2PLL, MMPLL,
WEDMCUPLL, NET1PLL and MPLL) follow MediaTek's TF-A [1][2].
[1] https://github.com/mtk-openwrt/arm-trusted-firmware/blob/a229810586d8/plat/mediatek/mt7986/drivers/pll/pll.c
[2] https://github.com/mtk-openwrt/arm-trusted-firmware/blob/a229810586d8/plat/mediatek/mt7986/drivers/pll/pll.h
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