MediaTek SoCs split their clock tree over several controllers built from
the same blocks. Add a base driver that maps a controller's registers
and registers its table of clocks, and the node types the tables use:
- PLL with the MT7986 register layout: the rate is read from the frequency control word and the post divider set by firmware. Gating follows the power up, isolation, enable and reset bar sequence. The rate cannot be changed.
- Mux with set/clear registers, an optional gate bit and an optional update latch.
- Gate with set, clear and status registers.
Clocks of other controllers are linked clocks, so the registration order
does not matter. A registration failure, including a mux selection the
table does not describe, panics, since nodes cannot be unregistered.
Clocks marked CLK_NODE_CANNOT_STOP (CPU, bus, DRAM) are enabled once at
attach and never released, because the flag alone does not keep their
parents running. The controllers attach after the fixed clocks and in
dependency order, so the parents exist by then. Failing to enable one
panics.
A controller can also be a reset controller, with banks of assert,
deassert and status registers. Only reset ids from the DT binding are
accepted.
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