The QoS core is used with the 64 bits descriptor address scheme, TDES1
and the *DLAR_HI registers holding the upper 32 bits. This only works
when the core was synthesized with a wider than 32 bits address bus. The
RK3568 GMAC for example has a 32 bits DMA: DMASBMR.EAME cannot be set and
the *DLAR_HI registers read back as zero. The DMA tags allowed any
address, so on systems with memory above 4GB the descriptor rings and the
mbufs could be allocated there and the core fetched descriptors and data
from the truncated addresses. Nothing could be sent or received.
Read the address width from the ADDR64 field of the MAC hardware feature 1
register, like Linux does, and limit the DMA tags to it. Memory that
cannot be reached is bounced by busdma.
Tested on a Quartz64 Model A with 8GB of RAM and on a NanoPi R5S.