Differential D60920

dwc: Program the DMA burst length of the QoS core
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Authored by manu on Tue, Oct 20, 5:34 PM.

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Referenced Files

	F177530781: D60920.1794643191.diff
	Fri, Nov 13, 7:59 AM

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Reviewers

br
mmel

Group Reviewers

Summary

dma4_init() set the 8xPBL mode bit but never wrote the programmable burst
lengths, which stay at the reset value of one beat, so the DMA engines issue
very short bursts. The TX and RX burst lengths are already parsed from the
device tree (snps,pbl, snps,txpbl, snps,rxpbl, default 8) for the older
core, use them here too.

Test Plan

Tested on Nanopi R5S :

driver tcp1_send tcp1_recv tcp4_send tcp4_recv

1 eqos 253/196 349/312 250/253 346/438
2 dwc 252/231 175/255 251/236 283/306
3 dwc 253/236 409/341 254/243 386/533
4 dwc 253/229 419/333 253/252 396/418
5 dwc 378/368 411/404 381/378 391/532 <- this commit

Diff Detail

Repository

rG FreeBSD src repository

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Build Status

Buildable 78438
Build 75321: arc lint + arc unit

Event Timeline

manu created this revision.Tue, Oct 20, 5:34 PM

Herald added a subscriber: imp. · View Herald TranscriptTue, Oct 20, 5:34 PM

manu requested review of this revision.Tue, Oct 20, 5:34 PM

Harbormaster completed remote builds in B78438: Diff 190428.Tue, Oct 20, 5:34 PM

manu added a parent revision: D60919: dwc: Do not report a negative number of output errors with the QoS core.Tue, Oct 20, 5:34 PM

manu added reviewers: arm64, br, mmel.Tue, Oct 20, 5:35 PM

manu edited the test plan for this revision. (Show Details)Tue, Oct 20, 5:38 PM

manu added a child revision: D61016: dwc: rockchip: Do not enable the same clock twice.Fri, Oct 30, 8:00 AM

Tested on Spacemit K3. Transfer speed improved significantly. Thanks!

This revision is now accepted and ready to land.Fri, Oct 30, 2:24 PM

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Path

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sys/

dev/

dwc/

5 lines

Diff 190428

sys/dev/dwc/dwc4_dma.c

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