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dwc: Configure the AXI request limits and mixed burst of the QoS core
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Authored by manu on Tue, Oct 20, 5:34 PM.
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Details

Reviewers
br
mmel
Group Reviewers
arm64
Summary

dma4_init() wrote the system bus mode register with only the burst length
and enhanced address bits, which left the maximum number of outstanding AXI
requests at its reset value of one and did not honour mixed burst. The
receive DMA could not keep up and dropped frames in the FIFO while the CPU
was mostly idle.

Parse the snps,axi-config node of the device tree (the maximum number of
outstanding read and write requests) with the other snps properties, and
program the limits, the hardware fields hold the limit minus one. Set the
mixed burst bit when snps,mixed-burst is present, as the eqos driver does.

Test Plan

Tested on Nanopi R5S:

driver tcp1_send tcp1_recv tcp4_send tcp4_recv

1 eqos 253/196 349/312 250/253 346/438
2 dwc 252/231 175/255 251/236 283/306
3 dwc 253/236 409/341 254/243 386/533 <- this commit
4 dwc 253/229 419/333 253/252 396/418
5 dwc 378/368 411/404 381/378 391/532

Diff Detail

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rG FreeBSD src repository
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Buildable 78436
Build 75319: arc lint + arc unit