Some Rockchip SoCs reference the same clock from several clock-names
properties. On the RK3568 both mac_clk_tx and clk_mac_speed reference
the same clock: SCLK_GMAC0_RX_TX on GMAC0 and SCLK_GMAC1_RX_TX on
GMAC1. So if_dwc_rk_init_clocks() enables that clock twice through two
different handles.
The clk framework then considers that the clock has more than one
consumer and refuses the rate change done by rk3568_set_speed() with
EBUSY, as the clock is not glitch-free.
Only enable clk_mac_speed if it is not the same clock as mac_clk_tx.