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Differential D41816

x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"
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Authored by olce on Sep 11 2023, 8:21 PM.
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Reviewers
kib
markj
emaste
Commits
rGe8d85401cd8d: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"
rG4fac67126e87: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"
rGd0c0dcf9db7e: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"
rG125bbadf6084: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"
Summary

They are a bit more informative than raw hexadecimal values.

While here, sort existing defines of bits for AMD MSRs to match the address
order.

Sponsored by: The FreeBSD Foundation

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rG FreeBSD src repository
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Tests Not Applicable

Event Timeline

olce created this revision.Sep 11 2023, 8:21 PM
Herald added a subscriber: imp. · View Herald TranscriptSep 11 2023, 8:21 PM
olce requested review of this revision.Sep 11 2023, 8:21 PM
Harbormaster completed remote builds in B53534: Diff 127241.Sep 11 2023, 8:21 PM
olce added reviewers: kib, markj, emaste.Sep 11 2023, 8:22 PM
olce added a child revision: D41817: x86: AMD Zen2: Zenbleed chicken bit mitigation.
kib accepted this revision.Sep 12 2023, 11:37 PM
This revision is now accepted and ready to land.Sep 12 2023, 11:37 PM
emaste accepted this revision.Sep 14 2023, 3:16 PM
Closed by commit rG125bbadf6084: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration" (authored by olce, committed by emaste). · Explain WhySep 14 2023, 3:30 PM
This revision was automatically updated to reflect the committed changes.
emaste added a commit: rG125bbadf6084: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration".
emaste added a commit: rGd0c0dcf9db7e: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration".Sep 25 2023, 1:46 PM
emaste added a commit: rG4fac67126e87: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration".Oct 10 2023, 1:37 PM
emaste added a commit: rGe8d85401cd8d: x86: Add defines for workaround bits in AMD's MSR "Decode Configuration".Oct 13 2023, 11:14 PM

Revision Contents
Changeset List

PathSize
sys/
amd64/
amd64/
5 lines
x86/
include/
9 lines

Diff 127390

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sys/amd64/amd64/initcpu.c

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sys/x86/include/specialreg.h

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