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x86: Add new Intel LPSS Uart driver
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Authored by manu on Wed, Nov 17, 1:58 PM.



Intel LPSS (Low Power Sub System) is a generic IP that can contain
either an I2C, SPI or UART controller.
They all share some common registers to help with frequency, dma etc ...
Add support for the UART part.
The PCI IDS for the Apollo and Gemini Lake were previously added to the
uart_bus_pci driver but even if they are detected they cannot be used with
just this and needs more glue.

Fixes: eaf00819bc ("Add support for Gemini Lake LPSS UARTs.")
Fixes: 8f1562430f ("Add Apollo Lake SIO/LPSS UARTs PCI IDs")

Sponsored by: Beckhoff Automation GmbH & Co. KG

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manu requested review of this revision.Wed, Nov 17, 1:58 PM
manu created this revision.

So there is two things that I'd like to fix before commiting this :

  • I would like dev/intel/lpss.c to be a driver and the uart_lpss a subclassed one but I don't know how to deal with the different softc (as a uart driver needs a uart softc as the first member of the softc and same thing with a subclassed driver).
  • I can't seems to be able to have a getty running on those uart, not sure why but I can connect to some arm board correctly. Is there anything else that a uart driver needs so getty is happy ?

Adding @kib as you commited the two commits that this "fixes".

Does this diff miss some sys/modules/ updates?

In D33033#746010, @kib wrote:

Does this diff miss some sys/modules/ updates?

Yeah I haven't done a module yet. added inline comments.

Uh, this is only 0x200 on Sunrise Point (and some later ones too I think). See D29249 (yeah, would be nice to use this in there). It's 0x800 on Lynx Point, 0x400 on Braswell and Bay Trail.


Mhm, there might be something that I missed in the linux driver then, will have another look tomorrow.


The linux driver structure is rather confusing. They don't have a proper centralized place for this, these base offsets are all over the place:


Yeah any mfd driver in linux is near to impossible to follow fully :)
But now I see what needs to be done here, thanks.


So I've look at most of the docs for the PCH and starting at Serie 100 (which goes with skylake) those registers are always at 0x200 (Named "Additional Registers" in the datasheet) and that's starting from this generation that the intel-lpss driver is used in Linux.
I don't plan to work on < skylake as I don't have hardware so intel lpss will also be for >= skylake for us.


Broadwell/LynxPoint is the only device I have for testing the Apple SPI input, I need LPSS on Broadwell, I have it working in D29249

I have been using a memory-mapped console (Apollo Lake E3950) by adding to /boot/loader.conf.d/console.conf:


Obviously, I prefer the direction this is heading to. I might be able to test on that platform.