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mvebu_gpio: fix gpio pin configuration update
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Authored by mw on Mar 3 2021, 6:35 PM.

Details

Summary

The GPIO pins have single corresponding bits in the
configuration registers. Hitherto accessor was
writing entire word with SYSCON_WRITE_4 instead of
doing a proper update with SYSCON_MODIFY_4.
Moreover the used mask had incorrect value.

Fix both issues and add the helper routine
gpio_pin_modify for accessing affected registers.

Diff Detail

Repository
R10 FreeBSD src repository
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Automatic diff as part of commit; lint not applicable.
Unit
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Event Timeline

mw requested review of this revision.Mar 3 2021, 6:35 PM

write is expected (moreover these are WO ->thus not suitable for SYSCON_MODIFY operation).

sys/arm/mv/mvebu_gpio.c
170

No, this change is wrong. GPIO have their own register for setting or clearing pin direction. Full register write is right at this place.

262

ditto.

299

ditto

mw marked 3 inline comments as done.Mar 3 2021, 9:46 PM

Confirmed with the specs and agree. Updating.

mw edited the summary of this revision. (Show Details)

@mmel you can commit this patch, it's basically your change. I only want it to be in the tree :)

This revision was not accepted when it landed; it landed in state Needs Review.Mar 4 2021, 4:55 PM
This revision was automatically updated to reflect the committed changes.