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- User Since
- Jul 4 2018, 7:23 PM (343 w, 3 d)
Yesterday
TL;DR I am annoyed at your desire to insert hacks into a core driver for all modern arm64 platforms and do not want to see good engineering practice thrown out the window in the name of making a specific piece of hardware "work" in the quickest way possible
Your unwillingness to try and actually understand the problem is your own choice, not mine. Adding a platform-specific quirk to ignore the inability to set something that the specification does not give implementations license to restrict is one thing, but doing it unilaterally for every platform is quite another thing and I wholeheartedly object to just disabling checks that get in the way with our current implementation on your hardware. We could quite easily have a real bug in our driver here, and in doing so we're just ignoring that. I also have absolutely no desire to encounter cache coherency bugs in future because of a change like this which just decides that cache coherency is something that can be ignored and everything will be fine, don't worry about it. I do not know what the implications of picking up a different firmware-chosen value here is and whether FreeBSD can in fact cope with it. Do you?
I also wrote the following on IRC a couple of weeks back:
The first hunk should not be necessary according to the specification, but if it helps your platform, does not regress others and is believed to be better anyway according to Andy then that's fine. The second hunk I do not believe should be committed.
Fri, Jan 31
Thu, Jan 30
Probably best to land this, since it's actually important for reproducibility, then we can update both to something else later that gives extra visibility into the build less urgently
Wed, Jan 29
Emit an error if MYMAKE is being messed with in any way
Tue, Jan 28
Mon, Jan 27
It doesn't need clocks, it needs one of clocks or clock-frequency. QEMU's virt board lists the latter, which is far simpler and preferable in a virtualisation setting. It also uses 3686400 as the frequency, which I believe lets the guest go up to 230400 baud. We should align with QEMU where possible in order to avoid surprises.
One could conceivably imagine the handles being small positive integers (nexus0 is 1, and so on) rather than using kernel addresses, so -1 seems more flexible IMO, and is generally a clear sentinel.
Fri, Jan 24
Thu, Jan 23
Wed, Jan 22
This doesn't seem to conform to the spec.
Tue, Jan 21
This always bugged me :)
Mon, Jan 20
Since this seems to be a saga that keeps on giving, I'm going to ask the important question to which the answer must have been no for every other commit for this, despite my comments on IRC:
Fri, Jan 17
Please put the rationale from your comment in the commit message, and mention that this may be improved in future to use the right DB (I intend to do that if nobody beats me to it).
Uh, why do we need that wrapper instead of just calling memchr itself?
Wed, Jan 15
Hm, this used to be required by POSIX but newer versions allow the implementation not to treat that as an error
Tue, Jan 14
Sat, Jan 11
Fri, Jan 10
I was going to suggest using the device_t-taking APIs instead, but then realised that doesn't work for the early case... bit sad but oh well.
(but please mention BSS in the commit message)
Thu, Jan 9
Mon, Jan 6
Sat, Jan 4
Dec 21 2024
Dec 20 2024
Dec 19 2024
Dec 18 2024
Wait so you put up a patch to disable Sstc before an alternative was provided?
Dec 17 2024
From grepping the tree this doesn't actually have any consequences currently, right, other than possible prints? The only real use I see is cpufreq, which we don't currently have for RISC-V.
Dec 16 2024
Dec 14 2024
Dec 13 2024
Dec 12 2024
Alternative proposal: https://reviews.freebsd.org/D48064
Also, please upload with full context
Do we really want one vm_cap_type entry per extension?
Dec 11 2024
Is there a reason to not do the right thing automatically via ROOT=... freebsd-version?
Dec 10 2024
Dec 9 2024
Nov 30 2024
Honestly we should instead be removing the use of intptr_t for hwreset, it's not a sensible type to use for an ID.
Nov 28 2024
Nov 21 2024
Ping @andrew
Perhaps worth mentioning in the commit message that RISC-V is unusual in allowing the TLB to cache invalid PTEs
Nov 20 2024
And amd64 has:
Also, perhaps worth pointing out arm64 does an unconditional intr_enable for the kernel too...
Presumably in practice the td_critnest check meant the interrupt enabling didn't matter, as spinlock_enter increments it? I assume there aren't many places where we disable interrupts without also being inside a critical section, so it would only be a problem if that sequence of code itself took a spurious fault.
Thanks, no more objections from me