(But also happy with the current diff if you'd rather go with that)

Ok, so long as everyone's in agreement that this ultimately needs to land in FreeBSD as a vendor import of a new upstream release, I'm happy

I don't see any of this upstream at https://gitlab.com/alfix/bsddialog, nor even as a merge request there?

Maybe for now it should just be "if ${_tool} is ld and a relative symlink to the same directory then wrap that too"?

You can't unconditionally add it though. For XLD it's probably ok to just check whether it's "ld" or not, but for LD I don't know what the right thing to do is.

Hm. If the link is absolute, we definitely don't need to do anything to it, and if the link is relative, well, who knows? We might already be linking it, copying it, adding our own wrapper, etc.

In D58050#1331122, @markj wrote:

In D58050#1331120, @jrtc27 wrote:

In D58050#1331116, @markj wrote:

@jrtc27 note that IN_IGNORED and IN_UNMOUNT aren't events that you explicitly ask for when you call inotify_add_watch(), they're generated automatically.

Uh, I think you do? I don't think you're meant to get them if not in the mask.

No, you're supposed to get them no matter what you asked for. The Linux man page describes them as flags set by the kernel in returned events. Note also that these flags don't belong to IN_ALL_EVENTS.

The untested https://termbin.com/tmhd is what my mental model is from reading the manpage and thinking about what sensible semantics would be. Maybe it should follow the existing locking discipline as in this patch, though I don't obviously see why that complexity is important for slightly shrinking the lock duration.

In D58050#1331116, @markj wrote:

@jrtc27 note that IN_IGNORED and IN_UNMOUNT aren't events that you explicitly ask for when you call inotify_add_watch(), they're generated automatically.

We may still end up with local diffs to include it in places that upstream doesn't, though

Linux lets you mprotect(PROT_MTE) to enable it. I don't know about disabling.

Would inverting it to PV_MTE_DIRTY not make more sense, as then the default state (and pages that aren't even mapped with tags enabled) is 0?

Implementation-wise it seems reasonable, but every time bsdinstall hardening gains an option the security world cries out in pain over having sensible defaults and good UX :')

Fixes: 7a58744fd0f1 ("Split out the attachment from the generic-ehci driver")

The change itself looks fine but I think the commit message needs rewriting. It is quite verbose on irrelevant details (like how bus_(space_)* foo work under the hood), and talks about data on the PCI bus (which is implementation, not architecture). Also the bug reference should follow the proper format (see tools/tools/git/hooks/prepare-commit-msg). Honestly the commit message would be better if it was entirely replaced with something like:

In D57422#1315673, @cperciva wrote:

In D57422#1315672, @jrtc27 wrote:

Hm, this'll break if building on Linux... don't know if GCE is one of the ones for which that's now supported, probably not, but a bit sad to have this

Oh, I didn't know our VM image building code supported cross-building. That would explain why the original patch (which was submitted from Google) was wrong though.

Hm, this'll break if building on Linux... don't know if GCE is one of the ones for which that's now supported, probably not, but a bit sad to have this

Hm, seems the current version is the same as the arm file, and now it's the same as the aarch64 one? I'm guessing copying from arm is how this came to be...

In D57379#1314791, @minsoochoo0122_proton.me wrote:

In D57379#1314786, @jrtc27 wrote:

In D57379#1314785, @minsoochoo0122_proton.me wrote:

In D57379#1314781, @jrtc27 wrote:

Having said that, what is the use case you have for these? Generally speaking you shouldn't be using sub-word atomics unless absolutely needed, since performance will be worse.

Just curious: do we have trampolines for sub-atomic operations at instruction level? Having them for Zabha or LDADD* would be great optimization opportunity.

I don't understand what your question means

The code has todo for Zabha support. I guess this means there will be implementation in future

if (has_zabha) {
    AMOADD.{B,H};
} else {
    load and fcmpset;
}

Oh, I think I used the term "trampoline" incorrectly here. I meant branching based on detection of Zabha (or equivalent on other ISA).

Back to my original question: How can we achieve this "special path" so processors with Zabha don't have severe performance impact?

In D57379#1314785, @minsoochoo0122_proton.me wrote:

In D57379#1314781, @jrtc27 wrote:

Having said that, what is the use case you have for these? Generally speaking you shouldn't be using sub-word atomics unless absolutely needed, since performance will be worse.

Just curious: do we have trampolines for sub-atomic operations at instruction level? Having them for Zabha or LDADD* would be great optimization opportunity.

In D57379#1314783, @zishun.yi.dev_gmail.com wrote:

In D57379#1314781, @jrtc27 wrote:

Having said that, what is the use case you have for these? Generally speaking you shouldn't be using sub-word atomics unless absolutely needed, since performance will be worse.

Ah, I didn't actually consider the performance before.
I added these to simplify the KASAN porting. KASAN needs to intercept these defines, but riscv doesn't have these definitions, so adding them ensures the KASAN common code won't be polluted by arch-specific code.

Having said that, what is the use case you have for these? Generally speaking you shouldn't be using sub-word atomics unless absolutely needed, since performance will be worse.

Surely these belong in atomic_subword.h or similar? They're not at all specific to RISC-V, and other architectures lack various of these.

In D57274#1312947, @emaste wrote:

I mean, sure, I guess, but what's the threat model here? I sure hope you trust the tarballs you're unpacking to install a system not to be malicious, otherwise what's the point?

I could come up with a contrived exploit scenario, but yes if someone controls the tarballs being unpacked during install it's likely much easier to just provide a trojaned binary.

This came to secteam and I thought "sure, why not."

I mean, sure, I guess, but what's the threat model here? I sure hope you trust the tarballs you're unpacking to install a system not to be malicious, otherwise what's the point?

In D56865#1312084, @arichardson wrote:

In D56865#1302643, @arichardson wrote:

In D56865#1302516, @jrtc27 wrote:

But won’t we have built elftoolchain strip in that case?

Seems like we didn't in my case, let me check if that is an explicit disable or the default. Or maybe we don't add the links anymore?

I get this error even with an explicit WITH_ELFTOOLCHAIN_BOOTSTRAP. Because I am also building with MK_LLVM_BINUTILS=no. So it sounds like either usr.bin/elfcopy needs another check for BOOTSTRAPPING, or we use this change (or possibly both fixes)? @emaste what do you think?

In D53910#1303910, @ziaee wrote:

In D53910#1303904, @jrtc27 wrote:

In D53910#1303893, @ziaee wrote:

In D53910#1303832, @jrtc27 wrote:

In D53910#1303533, @ziaee wrote:

Please understand that I am personally committed to seeing this website refresh land, however I am formally requesting changes proposed over email. I would like to propose the line objected to is replaced with "For over 30 years, this has been a grass roots project carried by passionate volunteers."

Firstly, for those of us not privy to this private email chain, what specifically is being objected to, and why?

The line "Check out the engagement driven by the FreeBSD Foundation on YouTube" is being objected to on the grounds that it is inappropriate for the "Community" box.

A social media presence dedicated to FreeBSD, by people who are involved in FreeBSD, that is an official FreeBSD-related organisation, and is engaging with people on the internet, is inappropriate for the "Community" section of the FreeBSD website how?..

The FreeBSD foundation is it's own entity, with it's own website. The Project is consists of a democratic system, which the Foundation exists completely separate and outside of.

In D53910#1303893, @ziaee wrote:

In D53910#1303832, @jrtc27 wrote:

In D53910#1303533, @ziaee wrote:

Please understand that I am personally committed to seeing this website refresh land, however I am formally requesting changes proposed over email. I would like to propose the line objected to is replaced with "For over 30 years, this has been a grass roots project carried by passionate volunteers."

Firstly, for those of us not privy to this private email chain, what specifically is being objected to, and why?

The line "Check out the engagement driven by the FreeBSD Foundation on YouTube" is being objected to on the grounds that it is inappropriate for the "Community" box.

The Vector spec does not require any ordering on the memory accesses performed, so a legal implementation could alternate which address faults and this would never make forward progress.

In D53910#1303533, @ziaee wrote:

Please understand that I am personally committed to seeing this website refresh land, however I am formally requesting changes proposed over email. I would like to propose the line objected to is replaced with "For over 30 years, this has been a grass roots project carried by passionate volunteers."

But won’t we have built elftoolchain strip in that case?

In D56717#1299142, @asomers wrote:

In D56717#1299128, @jrtc27 wrote:

Should this not do the same as 9134ed157388f3e34374322a5de06449a031f1ec?

It's not the same thing. That older revision changed the default interactive installation to pkgbase. What my change is is for the non-interactive installations. That is, the installations that the CD will do if you put an /etc/installerconfig file on the CD.

Should this not do the same as 9134ed157388f3e34374322a5de06449a031f1ec?

Oh, I always forget which way round -h and -n are. -n is the one you want, as we accept both as meaning the same thing, but coreutils only accepts -n.

These probably want -h too? pkg.pkg less interesting, but PKG_ALTABI surely that can go quite wrong if not?

Oh well I knew *that* one worked, I've run into this before even I think and added the missing semicolon, assuming it was my mistake (which it was, even if GNU sed is more friendly)

And indeed we do already handle the newline case correctly:

Not sure if this is actually a bug. POSIX says:

In D56551#1296024, @kajetan.puchalski_arm.com wrote:

As in we'd change the definition of the hypctx_sysreg enum itself? And then do "something" to special case it in the function? And have a new hypctx_sys_reg_cap that returned uintcap_t *? That seems like it could work. Though I've tagged @markj on this review as he did the initial adaptation of the proposed bhyve/arm64 code to Morello.

Something like that, yes. You could probably even do some preprocessor voodoo and make hypctx_sys_reg and the read/write functions macros that instantiate to the current function for normal registers, and to your hypctx_sys_reg_cap with its different return type for the capability-enabled ones.
As I've mentioned previously, currently all these functions and macros get compiled away to bare mrs & msr instructions. The "return type" is just there so that the compiler finds the right instruction.

Also, you could get rid of the need for specific read/write functions if you had something like:

I wish.. The read/write functions are just cosmetic and don't do anything at the moment, but they'll be necessary to handle certain architectural edge cases that'll come up when implementing support for nested virt. I'm just adding them ahead of time.
The reason I'm trying to funnel all reads and writes through these functions is so that when corrections need to be made to register reads and writes they only get made in one place.

As with the lib32 change, this needs a clear justification for why this default is being changed

What's the justification for changing this long-standing default? I don't see one in the summary. I'm not saying it's the wrong thing to do, but it needs to be clearly stated.

In D56551#1295970, @kajetan.puchalski_arm.com wrote:

I would really like to not land this patch before it's clear there's an *easy* path to making this work on Morello.

What's the remaining concern in that regard, then? Looking at the cheribsd github repo it already does a bunch of #if __has_feature(capabilities).
For any arbitrary register or group thereof, you can just add an if into hypctx_sys_reg and use whatever storage you like. In the VNCR page, in a different page, in the hypctx struct, whatever works.
It's specifically meant to be flexible in cases where a register needs "special" handling and needs to be put through a dedicated function and the like.

And see for example D55860 as things we continue to find by using it in anger downstream. I think we are by far the biggest user to date of bhyve on any form of arm64.

In D56551#1295949, @kajetan.puchalski_arm.com wrote:

In D56551#1295942, @jrtc27 wrote:

In D56551#1295771, @andrew wrote:

It looks like the two capability registers this change affects are elr_el1 and vbar_el1. Both of these have at least 128 bits of space before the next register, so storage shouldn't be a problem for Morello.

sp_el0, tpidr_el0, tpidrro_el0, and tpidr_el1 could be split into a new capability array when they are managed in a later change.

Also sp_el1 and tpidr_el2 in the VNCR space (why is tpidr_el2 even in there? I don't know if I want to know...). I would really like to not land this patch before it's clear there's an *easy* path to making this work on Morello. Breaking bhyve on Morello would be really quite unfortunate and hostile towards CheriBSD.

Does bhyve currently work on Morello?

In D56551#1295771, @andrew wrote:

It looks like the two capability registers this change affects are elr_el1 and vbar_el1. Both of these have at least 128 bits of space before the next register, so storage shouldn't be a problem for Morello.

sp_el0, tpidr_el0, tpidrro_el0, and tpidr_el1 could be split into a new capability array when they are managed in a later change.

In D56551#1294476, @kajetan.puchalski_arm.com wrote:

In D56551#1294463, @jrtc27 wrote:

This is really quite an obnoxious change to deal with for Morello, where some of these registers are 128-bit capabilities not 64-bit integers...

Which ones specifically?
Do you just mean it's harder to deal with because without this you'd just expand the sizes of registers in hypctx, whereas the VNCR layout doesn't have the same flexibility?

This is really quite an obnoxious change to deal with for Morello, where some of these registers are 128-bit capabilities not 64-bit integers...

I now understand why this case is there and am contemplating unifying the two paths so this condition can just be deleted even on non-PowerPC (it's more interesting on CHERI where even our ET_EXEC will have relocations for capabilities, but not integer addresses...), but for now this should be sufficient.

No support for ucontext.h posix API (looks like legacy)