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- May 9 2018, 1:01 AM (412 w, 23 h)
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This patch does not change what any of these Makefiles add to LDFLAGS. What is being changed by this patch to have these Makefile add their options to any existing contents of $LDFLAGS by using "LDFLAGS += ..." rather than discarding any existing contents of $LDFLAGS by using "LDFLAGS = ..." . I have no idea why any of these Makefiles want to add anything to LDFLAGS or if there is a better way to accomplish their goal, all I want to change is to add the "+'" in between "LDFLAGS" and "=".
Feb 26 2026
rebase to include recent changes to the tpm driver
Feb 17 2026
This patch does not introduce any of the things you mention, all of those things were already there. I agree that they look odd, and I can change them to be less odd in a separate change, but I wouldn't want to mix that in with the change at hand. Do you see any problem with the parts of the code that are actually changed by this patch?
Feb 16 2026
IOMMU support exists for amd64, but it is not enabled by default, and no bounce buffer memory is allocated by mpr attach with IOMMU support disabled. and mpr works fine without any IOMMU.
Feb 13 2026
replace the old fix with all new better fix
Feb 11 2026
The question I have is why any bounce buffer memory is being allocated at all by the creation of this tag. The code that sets up the template for creating buffer_dmat does not specify any constraints that would need bounce-buffering. Only low/highaddr and alignment can cause bounce-buffering to be needed, and the template does not set any of those. So the constraint that leads to the allocation of bounce-buffer memory must be inherited from some parent device. The only one I see that looks possibly relevant for your system is the one in opalpci_attach(), but that is supposedly only for POWER8 systems and your Blackbird system is supposed to be a POWER9 system. So I think it would help to find where the constraint that is triggering bounce-buffering is coming from.
Feb 2 2026
Oct 28 2025
Oct 13 2025
Sep 25 2025
Sep 2 2025
Sep 1 2025
Jul 30 2025
May 28 2025
Code change looks fine, commit comment has a typo (certian vs. certain).
The code change is fine, but the commit comment has several typos (appropraite vs. appropriate, phyiscal vs. physical, 2096 vs. 4096).
May 9 2025
this is fine as far as it goes, but the other places that already do "mpi3mr_atomic_dec(&tgtdev->block_io)" should also be converted to use the new mpi3mr_atomic_dec_if_not_zero().
Apr 23 2025
Apr 17 2025
Apr 14 2025
Ok, I didn't realize that "task management" always meant "target reset" here. Not waiting for in-progress commands makes sense in this context. Could you add a comment to the code explaining this?
Apr 11 2025
This change blocks new I/Os from being submitted while a task management command is in progress, but wouldn't you need to also wait for any in-progress I/Os to complete before submitting the task management command? I think you would need to wait for those if your goal is to avoid having the firmware processing I/O commands and task management commands together (which is what this change appears to be trying to do).
Apr 10 2025
I tried building with the new patch and found more problems:
in addition the changes you have here already, you'll also need to add the same line that you added to sys/conf/NOTES to sys/amd64/conf/GENERIC and sys/i386/conf/GENERIC.
Apr 9 2025
fix a bug I introduced when changing the calculation of cpi->maxio.
Apr 5 2025
fixed the typo in the subject and review title
Mar 28 2025
Mar 24 2025
I was going to do this this morning but you beat me to it. sorry for the noise.
Mar 19 2025
Feb 26 2025
removed unnecessary roundup() and fixed some PAGE_SIZE vs MPI3MR_4K_PGSZ confusion.
This patch had also tried to resolve some confusion between the OS PAGE_SIZE and the driver's MPI3MR_4K_PGSZ, but I got some cases wrong. I'll fix those in the next version of the patch as well.
Feb 21 2025
May 2 2024
Mar 20 2024
Feb 24 2024
There are some console messages printed by the early loading code, but these happen before the regular kernel printf code is initialized, so you can only see them if you enable "options EARLY_PRINTF" in your kernel config and also use "options UART_NS8250_EARLY_PORT=0x3f8" to set which serial port the early printf output should go to. (eg. the 0x3f8 in this example is com1). you also need to boot with "-v" to enable "bootverbose" messages for the ucode early load activity to be printed.
Feb 23 2024
Feb 22 2024
Feb 21 2024
Updated diff for latest review comments.
Feb 13 2024
Jan 29 2024
move the code copied from cpucontrol to a new file so that we can share it between the kernel and cpucontrol.
Jan 20 2024
Jan 19 2024
Jan 10 2024
I added the handling you requested for the loader blob containing all of the amd ucode files concatenated together.
updated patch with requested changes
Jan 4 2024
Jan 2 2024
Oct 13 2023
I agree, this msgbuftrigger thing is rather loosey-goosey. I'm just trying to have all the msgbuf paths achieve a consistent level of loosey-gooseyness.
