As I see, reading single byte at offset multiple to 4 this function still return 32-bit value, at next -- 24-bit, etc. Is this expected/acceptable behavior?

In D2469#45441, @mav wrote:

As I see, reading single byte at offset multiple to 4 this function still return 32-bit value, at next -- 24-bit, etc. Is this expected/acceptable behavior?

I am not sure that I understand the comment but here is an explanation of how it behaves after the patch:

Assuming that the AHCI register at offset 0x20 contains the value 0xDEADBEEF.

regoff size return pci_ahci_read()
0x20 1 0x00000000DEADBEEF
0x21 1 0x0000000000DEADBE
0x22 1 0x000000000000DEAD
0x23 1 0x00000000000000DE

• least significant 8-bits used by instruction emulation

0x20 2 0x00000000DEADBEEF
0x22 2 0x000000000000DEAD

• least significant 16-bits used by instruction emulation

0x20 4 0x00000000DEADBEEF

• least significant 32-bits used by instruction emulation

In D2469#45544, @neel wrote:

I am not sure that I understand the comment but here is an explanation of how it behaves after the patch:

I understand the behavior. Just was not sure what will trim extra bits. If all the consumers (instruction emulation code) do it correctly, then OK.