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Differential D45472

riscv: T-HEAD PBMT support
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Authored by mhorne on Jun 3 2024, 6:51 PM.
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markj
br
jrtc27
jhb
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riscv
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rGccbe9a9f732e: riscv: T-HEAD PBMT support
Summary

T-HEAD CPUs provide a spec-violating implementation of page-based memory
types, using PTE bits [63:59]. Add basic support for this "errata",
referred to in some places as an "extension".

Note that this change is not enough on its own, but a workaround is
needed for the bootstrap (locore) page tables as well.

Diff Detail

Repository
rG FreeBSD src repository
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Lint Passed
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No Test Coverage
Build Status
Buildable 58037
Build 54925: arc lint + arc unit

Event Timeline

mhorne created this revision.Jun 3 2024, 6:51 PM
Herald added a subscriber: imp. · View Herald TranscriptJun 3 2024, 6:51 PM
mhorne requested review of this revision.Jun 3 2024, 6:51 PM
Harbormaster completed remote builds in B58037: Diff 139385.Jun 3 2024, 6:51 PM
mhorne added a parent revision: D45471: riscv: Svpbmt extension support.Jun 3 2024, 6:51 PM
mhorne added a reviewer: jhb.Jun 3 2024, 6:52 PM
jhb added inline comments.Jun 6 2024, 4:42 PM
sys/riscv/include/pte.h
111–114

Is there no attribute for cacheable RAM, or should one of the labels here (PMA) use cacheable in the description?

sys/riscv/riscv/pmap.c
4771

If you pull memattr_mask down into the prior commit, I think you can just use it directly in this function instead of the local mask temporary?

mhorne updated this revision to Diff 140316.Jun 27 2024, 6:39 PM

Update according to C910 specification.

Tested on hardware (Allwinner D1), with workarounds applied, which boots until
late device probing.

Harbormaster completed remote builds in B58379: Diff 140316.Jun 27 2024, 6:39 PM
mhorne added inline comments.Jun 27 2024, 6:48 PM
sys/riscv/include/pte.h
126–129

For some reason I was getting strange (incorrect) bitmasks with the previous version. This is not final but it works...

sys/riscv/riscv/pmap.c
4771

Eventually, this function might be expanded to support changing the page protection bits as well, see pmap_change_props_locked() on amd64. In this case mask and bits will apply to more than the memory attributes. Therefore I think it is fine to leave it as is.

jhb accepted this revision as: jhb.Jul 30 2024, 4:44 PM
This revision is now accepted and ready to land.Jul 30 2024, 4:44 PM
mhorne updated this revision to Diff 146075.Nov 5 2024, 8:43 PM

Regenerate now that the series is more complete.

This revision now requires review to proceed.Nov 5 2024, 8:43 PM
Harbormaster completed remote builds in B60411: Diff 146075.Nov 5 2024, 8:43 PM
mhorne retitled this revision from [DRAFT/RFC] riscv: T-HEAD PBMT support to riscv: T-HEAD PBMT support.Nov 5 2024, 8:43 PM
mhorne edited the summary of this revision. (Show Details)
mhorne added a child revision: D47458: riscv: T-HEAD early locore workaround.
mhorne added a parent revision: D47455: riscv: add custom T-HEAD dcache ops.
mhorne marked an inline comment as done.
mhorne added inline comments.
sys/riscv/include/pte.h
111–114

I think this was a typo. Fixed now.

This revision was not accepted when it landed; it landed in state Needs Review.Nov 25 2024, 9:09 PM
Closed by commit rGccbe9a9f732e: riscv: T-HEAD PBMT support (authored by mhorne). · Explain Why
This revision was automatically updated to reflect the committed changes.
mhorne marked an inline comment as done.
mhorne added a commit: rGccbe9a9f732e: riscv: T-HEAD PBMT support.

Revision Contents
Changeset List

PathSize
sys/
riscv/
include/
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19 lines
riscv/
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22 lines

Diff 139385

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sys/riscv/include/md_var.h

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sys/riscv/include/pte.h

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sys/riscv/riscv/identcpu.c

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sys/riscv/riscv/pmap.c

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