arm64: Add an initial GICv5 driver

[andrew]

Summary

Add an initial driver for the GICv5 interrupt controller.

This provides host-only support for the GICv5 interrupt controller. It
is specified in the ARM-AES-0070 document & based on version 00eac0.

In the GICv5 there are 3 interrupt spaces: PPI, SPI, and LPI. Unlike
previous interrupt controllers they don't share a single interrupt
ID range, so PPI IRQ 1 and SPI IRQ 1 are different interrupts. There
is a common irqsrc stricture that encodes this information as it is
common across the interrupt types.

Unlike previous GIC versions there are no software generated interrupts
that can target a configurable collection of CPUs. These have been
replaced with LPIs, where each CPU will have one allocated for each
IPI type.

This driver handles the CPU interface and interrupt routing service
(IRS). The CPU interface provides the interface to manage and handle
interrupts, while the IRS handles routing LPIs and SPIs to the target
CPU.

Sponsored by: Arm Ltd

[ziaee]

Wow, this is cool! Can we have a manual? Even just a skeleton makes this so much more discoverable, like I did here:

https://cgit.freebsd.org/src/tree/share/man/man4/thunderbolt.4

Then, it's discoverable with apropos and I can list it in the hardware release notes.

sys/arm64/arm64/gicv5.c

1

Take a look at the preferred license for new files. This is also reflected in style(9).

https://docs.freebsd.org/en/articles/license-guide/

[andrew]

sys/arm64/arm64/gicv5.c

1

This file is based on an existing driver so the existing license is used.