arm64: Move setting TCR_HD to C code
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Authored by andrew on Wed, Nov 27, 6:10 PM.

Details

Reviewers

manu
markj
alc

Group Reviewers

ARM

Summary

To allow for it to be more selective when we enable it, e.g. if the
CPU has an erratum that prevents us from doing so, move the check for
setting TCR_HD to C.

Diff Detail

Repository

rG FreeBSD src repository

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Build Status

Buildable 60843
Build 57727: arc lint + arc unit

Event Timeline

andrew created this revision.Wed, Nov 27, 6:10 PM

Herald added a reviewer: manu. · View Herald TranscriptWed, Nov 27, 6:10 PM

Herald added subscribers: emaste, imp. · View Herald Transcript

andrew requested review of this revision.Wed, Nov 27, 6:10 PM

Harbormaster completed remote builds in B60843: Diff 147070.Wed, Nov 27, 6:10 PM

andrew added a child revision: D47809: arm64: Add a DBM errata workaround.Wed, Nov 27, 6:11 PM

andrew added reviewers: markj, alc.Wed, Nov 27, 6:14 PM

alc added inline comments.Thu, Nov 28, 6:12 PM

sys/arm64/arm64/pmap.c
1635	Is there a reason for omitting spaces here?

andrew added inline comments.Thu, Nov 28, 7:42 PM

sys/arm64/arm64/pmap.c
1635	Just to fit in 1 line

markj added inline comments.Fri, Nov 29, 2:20 PM

sys/arm64/arm64/locore.S
951	What's the reason for not setting TCR_HA in C as well?
sys/arm64/arm64/pmap.c
1635	IMO it would be nicer to just break the line.

andrew added inline comments.Fri, Nov 29, 2:58 PM

sys/arm64/arm64/locore.S
951	There are no errata where we need to selectively set TCR_HA so there is no need to move it.
sys/arm64/arm64/pmap.c
1635	I'd prefer to not change it as it will cause conflicts. This change so I can MFC the workaround faster than the cpu_feat code later in the stack.

alc accepted this revision.Sat, Dec 7, 6:15 PM

alc added inline comments.

sys/arm64/arm64/locore.S
951	Are any widely used cores affected?

This revision is now accepted and ready to land.Sat, Dec 7, 6:15 PM

alc added inline comments.Sat, Dec 7, 6:20 PM

sys/arm64/arm64/pmap.c
1635	I agree with Mark, but if it's expedient for getting a series of patches committed, then I'm okay with this. I assume that at a later point we can introduce a line break.

Later in this stack I am adding a new cpu feature framework (D47812) and changing this to use it (D47815)

sys/arm64/arm64/locore.S
951	The workarounds are added in D47809. The two cores affected are Cortex-A55 and some early Cortex-A510 revisions.
sys/arm64/arm64/pmap.c
1635	It looks like I fixed it in the next commit (D47809) as it removed the braces so the line isn't as long.