msun/riscv: expose fe{disable,enable}except
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Authored by brooks on Mar 12 2024, 10:47 PM.

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Reviewers

jrtc27
br
mhorne

Group Reviewers

riscv

Commits

rG1947a9383ec3: msun/riscv: expose fe{disable,enable}except

Summary

This is required for GCC to build. Play the Tier-2 card and don't care
about ABI disruption on soft-float, especially since we don't provide
such a target arch any more.

PR: 272759
Reported by: dgilbert@eicat.ca
Submitted by: jrtc27

Diff Detail

Repository

rG FreeBSD src repository

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Tests Not Applicable

Event Timeline

brooks created this revision.Mar 12 2024, 10:47 PM

Herald added a subscriber: imp. · View Herald TranscriptMar 12 2024, 10:47 PM

brooks requested review of this revision.Mar 12 2024, 10:47 PM

Harbormaster completed remote builds in B56568: Diff 135678.Mar 12 2024, 10:47 PM

brooks added a child revision: D44331: msun/riscv: limit exposure of fegetexcept.Mar 12 2024, 10:49 PM

By ABI break you mean for riscv64sf getting the old symbol versions? That architecture is dead, we should just delete the dead code in the header.

In D44333#1011114, @jrtc27 wrote:

By ABI break you mean for riscv64sf getting the old symbol versions? That architecture is dead, we should just delete the dead code in the header.

OK, I'll do that is a separate commit.

brooks added reviewers: br, mhorne.Mar 15 2024, 11:16 PM

This revision was not accepted when it landed; it landed in state Needs Review.Mar 21 2024, 11:50 PM

Closed by commit rG1947a9383ec3: msun/riscv: expose fe{disable,enable}except (authored by brooks). · Explain Why

This revision was automatically updated to reflect the committed changes.

brooks added a commit: rG1947a9383ec3: msun/riscv: expose fe{disable,enable}except.