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arm64: Add explicit barrier after address translation instruction
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Authored by scottph on Mar 24 2022, 5:10 PM.
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Details

Summary

Following ARMARM sec D5.2.11, which says:

Where an instruction results in an update to a System register,
as is the case with the AT * address translation instructions,
explicit synchronization must be performed before the result is
guaranteed to be visible to subsequent direct reads of the
PAR_EL1.

Sponsored by: Ampere Computing

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